blob: e1f5a7381357035264fcc7cf35adbd8507e0ec28 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warren41b68382011-01-27 10:58:05 +00002/*
Thierry Redingce7eb162019-04-15 11:32:25 +02003 * (C) Copyright 2010-2019
Tom Warren41b68382011-01-27 10:58:05 +00004 * NVIDIA Corporation <www.nvidia.com>
Tom Warren41b68382011-01-27 10:58:05 +00005 */
6
7#ifndef _PMC_H_
8#define _PMC_H_
9
Simon Glass4dcacfc2020-05-10 11:40:13 -060010#ifndef __ASSEMBLY__
11#include <linux/bitops.h>
12#endif
13
Tom Warren41b68382011-01-27 10:58:05 +000014/* Power Management Controller (APBDEV_PMC_) registers */
15struct pmc_ctlr {
16 uint pmc_cntrl; /* _CNTRL_0, offset 00 */
17 uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */
18 uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */
19 uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */
20 uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */
21 uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */
22 uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */
23 uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */
24 uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */
25 uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */
26 uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */
Stephen Warren78452c32014-01-24 10:23:02 -070027#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
Tom Warren41b68382011-01-27 10:58:05 +000028 uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */
Stephen Warren78452c32014-01-24 10:23:02 -070029#else
30 uint pmc_clamp_status; /* _CLAMP_STATUS_0, offset 2C */
31#endif
Tom Warren41b68382011-01-27 10:58:05 +000032 uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */
33 uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */
34 uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */
35 uint pmc_pwrgood_timer; /* _PWRGOOD_TIMER_0, offset 3C */
36 uint pmc_blink_timer; /* _BLINK_TIMER_0, offset 40 */
37 uint pmc_no_iopower; /* _NO_IOPOWER_0, offset 44 */
38 uint pmc_pwr_det; /* _PWR_DET_0, offset 48 */
39 uint pmc_pwr_det_latch; /* _PWR_DET_LATCH_0, offset 4C */
40
41 uint pmc_scratch0; /* _SCRATCH0_0, offset 50 */
42 uint pmc_scratch1; /* _SCRATCH1_0, offset 54 */
43 uint pmc_scratch2; /* _SCRATCH2_0, offset 58 */
44 uint pmc_scratch3; /* _SCRATCH3_0, offset 5C */
45 uint pmc_scratch4; /* _SCRATCH4_0, offset 60 */
46 uint pmc_scratch5; /* _SCRATCH5_0, offset 64 */
47 uint pmc_scratch6; /* _SCRATCH6_0, offset 68 */
48 uint pmc_scratch7; /* _SCRATCH7_0, offset 6C */
49 uint pmc_scratch8; /* _SCRATCH8_0, offset 70 */
50 uint pmc_scratch9; /* _SCRATCH9_0, offset 74 */
51 uint pmc_scratch10; /* _SCRATCH10_0, offset 78 */
52 uint pmc_scratch11; /* _SCRATCH11_0, offset 7C */
53 uint pmc_scratch12; /* _SCRATCH12_0, offset 80 */
54 uint pmc_scratch13; /* _SCRATCH13_0, offset 84 */
55 uint pmc_scratch14; /* _SCRATCH14_0, offset 88 */
56 uint pmc_scratch15; /* _SCRATCH15_0, offset 8C */
57 uint pmc_scratch16; /* _SCRATCH16_0, offset 90 */
58 uint pmc_scratch17; /* _SCRATCH17_0, offset 94 */
59 uint pmc_scratch18; /* _SCRATCH18_0, offset 98 */
60 uint pmc_scratch19; /* _SCRATCH19_0, offset 9C */
61 uint pmc_scratch20; /* _SCRATCH20_0, offset A0 */
62 uint pmc_scratch21; /* _SCRATCH21_0, offset A4 */
63 uint pmc_scratch22; /* _SCRATCH22_0, offset A8 */
64 uint pmc_scratch23; /* _SCRATCH23_0, offset AC */
65
66 uint pmc_secure_scratch0; /* _SECURE_SCRATCH0_0, offset B0 */
67 uint pmc_secure_scratch1; /* _SECURE_SCRATCH1_0, offset B4 */
68 uint pmc_secure_scratch2; /* _SECURE_SCRATCH2_0, offset B8 */
69 uint pmc_secure_scratch3; /* _SECURE_SCRATCH3_0, offset BC */
70 uint pmc_secure_scratch4; /* _SECURE_SCRATCH4_0, offset C0 */
71 uint pmc_secure_scratch5; /* _SECURE_SCRATCH5_0, offset C4 */
72
73 uint pmc_cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, offset C8 */
74 uint pmc_cpupwroff_timer; /* _CPUPWROFF_TIMER_0, offset CC */
75 uint pmc_pg_mask; /* _PG_MASK_0, offset D0 */
76 uint pmc_pg_mask_1; /* _PG_MASK_1_0, offset D4 */
77 uint pmc_auto_wake_lvl; /* _AUTO_WAKE_LVL_0, offset D8 */
78 uint pmc_auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, offset DC */
79 uint pmc_wake_delay; /* _WAKE_DELAY_0, offset E0 */
80 uint pmc_pwr_det_val; /* _PWR_DET_VAL_0, offset E4 */
81 uint pmc_ddr_pwr; /* _DDR_PWR_0, offset E8 */
82 uint pmc_usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, offset EC */
83 uint pmc_usb_ao; /* _USB_AO_0, offset F0 */
84 uint pmc_crypto_op; /* _CRYPTO_OP__0, offset F4 */
85 uint pmc_pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, offset F8 */
86
87 uint pmc_scratch24; /* _SCRATCH24_0, offset FC */
88 uint pmc_scratch25; /* _SCRATCH24_0, offset 100 */
89 uint pmc_scratch26; /* _SCRATCH24_0, offset 104 */
90 uint pmc_scratch27; /* _SCRATCH24_0, offset 108 */
91 uint pmc_scratch28; /* _SCRATCH24_0, offset 10C */
92 uint pmc_scratch29; /* _SCRATCH24_0, offset 110 */
93 uint pmc_scratch30; /* _SCRATCH24_0, offset 114 */
94 uint pmc_scratch31; /* _SCRATCH24_0, offset 118 */
95 uint pmc_scratch32; /* _SCRATCH24_0, offset 11C */
96 uint pmc_scratch33; /* _SCRATCH24_0, offset 120 */
97 uint pmc_scratch34; /* _SCRATCH24_0, offset 124 */
98 uint pmc_scratch35; /* _SCRATCH24_0, offset 128 */
99 uint pmc_scratch36; /* _SCRATCH24_0, offset 12C */
100 uint pmc_scratch37; /* _SCRATCH24_0, offset 130 */
101 uint pmc_scratch38; /* _SCRATCH24_0, offset 134 */
102 uint pmc_scratch39; /* _SCRATCH24_0, offset 138 */
103 uint pmc_scratch40; /* _SCRATCH24_0, offset 13C */
104 uint pmc_scratch41; /* _SCRATCH24_0, offset 140 */
105 uint pmc_scratch42; /* _SCRATCH24_0, offset 144 */
106
107 uint pmc_bo_mirror0; /* _BOUNDOUT_MIRROR0_0, offset 148 */
108 uint pmc_bo_mirror1; /* _BOUNDOUT_MIRROR1_0, offset 14C */
109 uint pmc_bo_mirror2; /* _BOUNDOUT_MIRROR2_0, offset 150 */
110 uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */
111 uint pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
112 uint pmc_gate; /* _GATE_0, offset 15C */
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700113 /* The following fields are in Tegra124 and later only */
114 uint pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */
115 uint pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */
116 uint pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */
117 uint pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */
118 uint pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */
119 uint pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */
120 uint pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */
121 uint pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */
122 uint pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */
123 uint pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */
124 uint pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */
125 uint pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */
126 uint pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */
127 uint pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */
128 uint pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */
129 uint pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */
130 uint pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */
131 uint pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */
132 uint pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */
133 uint pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */
134 uint pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */
135 uint pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */
136 uint pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */
137 uint pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */
138 uint pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */
139 uint pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */
140 uint pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */
141 uint pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */
142
143 uint pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */
144 uint pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */
145 uint pmc_reserved0; /* _RESERVED, offset 1D8 */
146 uint pmc_pllm_wb0_ovrride_frq; /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */
147 uint pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */
148 uint pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */
149 uint pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */
150 uint pmc_utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */
151 uint pmc_utmip_uhsic_saved_st; /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */
152 uint pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */
153 uint pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */
154 uint pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */
155
156 uint pmc_todo_0[9]; /* offset 200-220 */
157 uint pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */
158 uint pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */
159 uint pmc_scratch43; /* _SCRATCH43_0, offset 22C */
160 uint pmc_scratch44; /* _SCRATCH44_0, offset 230 */
161 uint pmc_scratch45;
162 uint pmc_scratch46;
163 uint pmc_scratch47;
164 uint pmc_scratch48;
165 uint pmc_scratch49;
166 uint pmc_scratch50;
167 uint pmc_scratch51;
168 uint pmc_scratch52;
169 uint pmc_scratch53;
170 uint pmc_scratch54;
171 uint pmc_scratch55; /* _SCRATCH55_0, offset 25C */
172 uint pmc_scratch0_eco; /* _SCRATCH0_ECO_0, offset 260 */
173 uint pmc_por_dpd_ctrl; /* _POR_DPD_CTRL_0, offset 264 */
174 uint pmc_scratch2_eco; /* _SCRATCH2_ECO_0, offset 268 */
175 uint pmc_todo_1[17]; /* TODO: 26C ~ 2AC */
176 uint pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */
177 uint pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */
178 uint pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */
179 uint pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */
180 uint pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */
181 uint pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */
182 uint pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */
183 uint pmc_todo_3[13]; /* TODO: 2CC ~ 2FC */
184 uint pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */
185 uint pmc_secure_scratch9;
186 uint pmc_secure_scratch10;
187 uint pmc_secure_scratch11;
188 uint pmc_secure_scratch12;
189 uint pmc_secure_scratch13;
190 uint pmc_secure_scratch14;
191 uint pmc_secure_scratch15;
192 uint pmc_secure_scratch16;
193 uint pmc_secure_scratch17;
194 uint pmc_secure_scratch18;
195 uint pmc_secure_scratch19;
196 uint pmc_secure_scratch20;
197 uint pmc_secure_scratch21;
198 uint pmc_secure_scratch22;
199 uint pmc_secure_scratch23;
200 uint pmc_secure_scratch24; /* _SECURE_SCRATCH24_0, offset 340 */
201 uint pmc_secure_scratch25;
202 uint pmc_secure_scratch26;
203 uint pmc_secure_scratch27;
204 uint pmc_secure_scratch28;
205 uint pmc_secure_scratch29;
206 uint pmc_secure_scratch30;
207 uint pmc_secure_scratch31;
208 uint pmc_secure_scratch32;
209 uint pmc_secure_scratch33;
210 uint pmc_secure_scratch34;
211 uint pmc_secure_scratch35; /* _SECURE_SCRATCH35_0, offset 36C */
212
213 uint pmc_reserved1[52]; /* RESERVED: 370 ~ 43C */
214 uint pmc_cntrl2; /* _CNTRL2_0, offset 440 */
215 uint pmc_reserved2[6]; /* RESERVED: 444 ~ 458 */
216 uint pmc_io_dpd3_req; /* _IO_DPD3_REQ_0, offset 45c */
217 uint pmc_io_dpd3_stat; /* _IO_DPD3_STATUS_0, offset 460 */
218 uint pmc_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 464 */
219 uint pmc_reserved3[102]; /* RESERVED: 468 ~ 5FC */
220
221 uint pmc_scratch56; /* _SCRATCH56_0, offset 600 */
222 uint pmc_scratch57;
223 uint pmc_scratch58;
224 uint pmc_scratch59;
225 uint pmc_scratch60;
226 uint pmc_scratch61;
227 uint pmc_scratch62;
228 uint pmc_scratch63;
229 uint pmc_scratch64;
230 uint pmc_scratch65;
231 uint pmc_scratch66;
232 uint pmc_scratch67;
233 uint pmc_scratch68;
234 uint pmc_scratch69;
235 uint pmc_scratch70;
236 uint pmc_scratch71;
237 uint pmc_scratch72;
238 uint pmc_scratch73;
239 uint pmc_scratch74;
240 uint pmc_scratch75;
241 uint pmc_scratch76;
242 uint pmc_scratch77;
243 uint pmc_scratch78;
244 uint pmc_scratch79;
245 uint pmc_scratch80;
246 uint pmc_scratch81;
247 uint pmc_scratch82;
248 uint pmc_scratch83;
249 uint pmc_scratch84;
250 uint pmc_scratch85;
251 uint pmc_scratch86;
252 uint pmc_scratch87;
253 uint pmc_scratch88;
254 uint pmc_scratch89;
255 uint pmc_scratch90;
256 uint pmc_scratch91;
257 uint pmc_scratch92;
258 uint pmc_scratch93;
259 uint pmc_scratch94;
260 uint pmc_scratch95;
261 uint pmc_scratch96;
262 uint pmc_scratch97;
263 uint pmc_scratch98;
264 uint pmc_scratch99;
265 uint pmc_scratch100;
266 uint pmc_scratch101;
267 uint pmc_scratch102;
268 uint pmc_scratch103;
269 uint pmc_scratch104;
270 uint pmc_scratch105;
271 uint pmc_scratch106;
272 uint pmc_scratch107;
273 uint pmc_scratch108;
274 uint pmc_scratch109;
275 uint pmc_scratch110;
276 uint pmc_scratch111;
277 uint pmc_scratch112;
278 uint pmc_scratch113;
279 uint pmc_scratch114;
280 uint pmc_scratch115;
281 uint pmc_scratch116;
282 uint pmc_scratch117;
283 uint pmc_scratch118;
284 uint pmc_scratch119;
285 uint pmc_scratch1_eco; /* offset 700 */
Tom Warren41b68382011-01-27 10:58:05 +0000286};
287
Tom Warren112a1882011-04-14 12:18:06 +0000288#define CPU_PWRED 1
289#define CPU_CLMP 1
290
291#define PARTID_CP 0xFFFFFFF8
292#define START_CP (1 << 8)
293
294#define CPUPWRREQ_OE (1 << 16)
Tom Warrenc47e7172013-01-28 13:32:07 +0000295#define CPUPWRREQ_POL (1 << 15)
296
Stephen Warren45917e12014-01-24 12:46:08 -0700297#define CRAIL 0
298#define CE0 14
299#define C0NC 15
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700300#define SOR 17
Tom Warren112a1882011-04-14 12:18:06 +0000301
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700302#define PMC_XOFS_SHIFT 1
303#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
304
Stephen Warrenc952f6e2014-02-03 14:03:25 -0700305#if defined(CONFIG_TEGRA114)
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700306#define TIMER_MULT_SHIFT 0
307#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
308#define TIMER_MULT_CPU_SHIFT 2
309#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700310#elif defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
Stephen Warrenc952f6e2014-02-03 14:03:25 -0700311#define TIMER_MULT_SHIFT 0
312#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT)
313#define TIMER_MULT_CPU_SHIFT 3
314#define TIMER_MULT_CPU_MASK (7 << TIMER_MULT_CPU_SHIFT)
315#endif
316
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700317#define MULT_1 0
318#define MULT_2 1
319#define MULT_4 2
320#define MULT_8 3
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700321#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
Stephen Warrenc952f6e2014-02-03 14:03:25 -0700322#define MULT_16 4
323#endif
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700324
325#define AMAP_WRITE_SHIFT 20
326#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT)
327
328/* SEC_DISABLE_0, 0x04 */
329#define SEC_DISABLE_WRITE0_ON (1 << 4)
330#define SEC_DISABLE_READ0_ON (1 << 5)
331#define SEC_DISABLE_WRITE1_ON (1 << 6)
332#define SEC_DISABLE_READ1_ON (1 << 7)
333#define SEC_DISABLE_WRITE2_ON (1 << 8)
334#define SEC_DISABLE_READ2_ON (1 << 9)
335#define SEC_DISABLE_WRITE3_ON (1 << 10)
336#define SEC_DISABLE_READ3_ON (1 << 11)
337#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20)
338
339/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */
340#define PWRGATE_TOGGLE_PARTID_CRAIL 0
341#define PWRGATE_TOGGLE_PARTID_TD 1
342#define PWRGATE_TOGGLE_PARTID_VE 2
343#define PWRGATE_TOGGLE_PARTID_PCX 3
344#define PWRGATE_TOGGLE_PARTID_VDE 4
345#define PWRGATE_TOGGLE_PARTID_L2C 5
346#define PWRGATE_TOGGLE_PARTID_MPE 6
347#define PWRGATE_TOGGLE_PARTID_HEG 7
348#define PWRGATE_TOGGLE_PARTID_SAX 8
349#define PWRGATE_TOGGLE_PARTID_CE1 9
350#define PWRGATE_TOGGLE_PARTID_CE2 10
351#define PWRGATE_TOGGLE_PARTID_CE3 11
352#define PWRGATE_TOGGLE_PARTID_CELP 12
353#define PWRGATE_TOGGLE_PARTID_CE0 14
354#define PWRGATE_TOGGLE_PARTID_C0NC 15
355#define PWRGATE_TOGGLE_PARTID_C1NC 16
356#define PWRGATE_TOGGLE_PARTID_SOR 17
357#define PWRGATE_TOGGLE_PARTID_DIS 18
358#define PWRGATE_TOGGLE_PARTID_DISB 19
359#define PWRGATE_TOGGLE_PARTID_XUSBA 20
360#define PWRGATE_TOGGLE_PARTID_XUSBB 21
361#define PWRGATE_TOGGLE_PARTID_XUSBC 22
362#define PWRGATE_TOGGLE_PARTID_VIC 23
363#define PWRGATE_TOGGLE_PARTID_IRAM 24
364#define PWRGATE_TOGGLE_START (1 << 8)
365
366/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */
367#define PWRGATE_STATUS_CRAIL_ENABLE (1 << 0)
368#define PWRGATE_STATUS_TD_ENABLE (1 << 1)
369#define PWRGATE_STATUS_VE_ENABLE (1 << 2)
370#define PWRGATE_STATUS_PCX_ENABLE (1 << 3)
371#define PWRGATE_STATUS_VDE_ENABLE (1 << 4)
372#define PWRGATE_STATUS_L2C_ENABLE (1 << 5)
373#define PWRGATE_STATUS_MPE_ENABLE (1 << 6)
374#define PWRGATE_STATUS_HEG_ENABLE (1 << 7)
375#define PWRGATE_STATUS_SAX_ENABLE (1 << 8)
376#define PWRGATE_STATUS_CE1_ENABLE (1 << 9)
377#define PWRGATE_STATUS_CE2_ENABLE (1 << 10)
378#define PWRGATE_STATUS_CE3_ENABLE (1 << 11)
379#define PWRGATE_STATUS_CELP_ENABLE (1 << 12)
380#define PWRGATE_STATUS_CE0_ENABLE (1 << 14)
381#define PWRGATE_STATUS_C0NC_ENABLE (1 << 15)
382#define PWRGATE_STATUS_C1NC_ENABLE (1 << 16)
383#define PWRGATE_STATUS_SOR_ENABLE (1 << 17)
384#define PWRGATE_STATUS_DIS_ENABLE (1 << 18)
385#define PWRGATE_STATUS_DISB_ENABLE (1 << 19)
386#define PWRGATE_STATUS_XUSBA_ENABLE (1 << 20)
387#define PWRGATE_STATUS_XUSBB_ENABLE (1 << 21)
388#define PWRGATE_STATUS_XUSBC_ENABLE (1 << 22)
389#define PWRGATE_STATUS_VIC_ENABLE (1 << 23)
390#define PWRGATE_STATUS_IRAM_ENABLE (1 << 24)
391
392/* APBDEV_PMC_CNTRL2_0 0x440 */
393#define HOLD_CKE_LOW_EN (1 << 12)
394
Thierry Redingce7eb162019-04-15 11:32:25 +0200395/* PMC read/write functions */
396u32 tegra_pmc_readl(unsigned long offset);
397void tegra_pmc_writel(u32 value, unsigned long offset);
398
399#define PMC_CNTRL 0x0
400#define PMC_CNTRL_MAIN_RST BIT(4)
401
402#if IS_ENABLED(CONFIG_TEGRA186)
403# define PMC_SCRATCH0 0x32000
404#else
405# define PMC_SCRATCH0 0x00050
406#endif
407
408/* for secure PMC */
409#define TEGRA_SMC_PMC 0xc2fffe00
410#define TEGRA_SMC_PMC_READ 0xaa
411#define TEGRA_SMC_PMC_WRITE 0xbb
412
Tom Warren41b68382011-01-27 10:58:05 +0000413#endif /* PMC_H */