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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Angelo Dureghello67c4e482017-08-07 01:17:18 +02002/*
3 * Sysam stmark2 board configuration
4 *
5 * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
Angelo Dureghello67c4e482017-08-07 01:17:18 +02006 */
7
8#ifndef __STMARK2_CONFIG_H
9#define __STMARK2_CONFIG_H
10
Tom Rini6a5dccc2022-11-16 13:10:41 -050011#define CFG_SYS_UART_PORT 0
Angelo Dureghello67c4e482017-08-07 01:17:18 +020012
13#define LDS_BOARD_TEXT \
14 board/sysam/stmark2/sbf_dram_init.o (.text*)
15
Tom Rinic9edebe2022-12-04 10:03:50 -050016#define CFG_EXTRA_ENV_SETTINGS \
Angelo Dureghello67c4e482017-08-07 01:17:18 +020017 "kern_size=0x700000\0" \
18 "loadaddr=0x40001000\0" \
19 "-(rootfs)\0" \
20 "update_uboot=loady ${loadaddr}; " \
21 "sf probe 0:1 50000000; " \
22 "sf erase 0 0x80000; " \
23 "sf write ${loadaddr} 0 ${filesize}\0" \
24 "update_kernel=loady ${loadaddr}; " \
25 "setenv kern_size ${filesize}; saveenv; " \
26 "sf probe 0:1 50000000; " \
27 "sf erase 0x100000 0x700000; " \
28 "sf write ${loadaddr} 0x100000 ${filesize}\0" \
29 "update_rootfs=loady ${loadaddr}; " \
30 "sf probe 0:1 50000000; " \
31 "sf erase 0x00800000 0x100000; " \
32 "sf write ${loadaddr} 0x00800000 ${filesize}\0" \
33 ""
34
Tom Rini6a5dccc2022-11-16 13:10:41 -050035#define CFG_SYS_SBFHDR_SIZE 0x7
Angelo Dureghello67c4e482017-08-07 01:17:18 +020036
Angelo Dureghello67c4e482017-08-07 01:17:18 +020037/* Input, PCI, Flexbus, and VCO */
Angelo Dureghello67c4e482017-08-07 01:17:18 +020038
39#define CONFIG_PRAM 2048 /* 2048 KB */
Angelo Dureghello67c4e482017-08-07 01:17:18 +020040
Tom Rini6a5dccc2022-11-16 13:10:41 -050041#define CFG_SYS_MBAR 0xFC000000
Angelo Dureghello67c4e482017-08-07 01:17:18 +020042
43/*
44 * Definitions for initial stack pointer and data area (in internal SRAM)
45 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050046#define CFG_SYS_INIT_RAM_ADDR 0x80000000
Angelo Dureghello67c4e482017-08-07 01:17:18 +020047/* End of used area in internal SRAM */
Tom Rini6a5dccc2022-11-16 13:10:41 -050048#define CFG_SYS_INIT_RAM_SIZE 0x10000
49#define CFG_SYS_INIT_RAM_CTRL 0x221
50#define CFG_SYS_INIT_SP_OFFSET ((CFG_SYS_INIT_RAM_SIZE - \
Angelo Dureghello67c4e482017-08-07 01:17:18 +020051 GENERATED_GBL_DATA_SIZE) - 32)
Tom Rini6a5dccc2022-11-16 13:10:41 -050052#define CFG_SYS_SBFHDR_DATA_OFFSET (CFG_SYS_INIT_RAM_SIZE - 32)
Angelo Dureghello67c4e482017-08-07 01:17:18 +020053
54/*
55 * Start addresses for the final memory configuration
56 * (Set up by the startup code)
Tom Rinibb4dd962022-11-16 13:10:37 -050057 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
Angelo Dureghello67c4e482017-08-07 01:17:18 +020058 */
Tom Rinibb4dd962022-11-16 13:10:37 -050059#define CFG_SYS_SDRAM_BASE 0x40000000
60#define CFG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
Angelo Dureghello67c4e482017-08-07 01:17:18 +020061
Tom Rini6a5dccc2022-11-16 13:10:41 -050062#define CFG_SYS_DRAM_TEST
Angelo Dureghello67c4e482017-08-07 01:17:18 +020063
Angelo Dureghello67c4e482017-08-07 01:17:18 +020064/* Reserve 256 kB for Monitor */
Angelo Dureghello67c4e482017-08-07 01:17:18 +020065
66/*
67 * For booting Linux, the board info and command line data
68 * have to be in the first 8 MB of memory, since this is
69 * the maximum mapped by the Linux kernel during initialization ??
70 */
71/* Initial Memory map for Linux */
Tom Rini6a5dccc2022-11-16 13:10:41 -050072#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
Tom Rinibb4dd962022-11-16 13:10:37 -050073 (CFG_SYS_SDRAM_SIZE << 20))
Angelo Dureghello67c4e482017-08-07 01:17:18 +020074
75/* Configuration for environment
76 * Environment is embedded in u-boot in the second sector of the flash
77 */
78
Angelo Dureghello67c4e482017-08-07 01:17:18 +020079/* Cache Configuration */
Tom Rini6a5dccc2022-11-16 13:10:41 -050080#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
81 CFG_SYS_INIT_RAM_SIZE - 8)
82#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
83 CFG_SYS_INIT_RAM_SIZE - 4)
84#define CFG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
85#define CFG_SYS_DCACHE_INV (CF_CACR_DCINVA)
86#define CFG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \
Tom Rinibb4dd962022-11-16 13:10:37 -050087 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
Angelo Dureghello67c4e482017-08-07 01:17:18 +020088 CF_ACR_EN | CF_ACR_SM_ALL)
Tom Rini6a5dccc2022-11-16 13:10:41 -050089#define CFG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
Angelo Dureghello67c4e482017-08-07 01:17:18 +020090 CF_CACR_ICINVA | CF_CACR_EUSP)
Tom Rini6a5dccc2022-11-16 13:10:41 -050091#define CFG_SYS_CACHE_DCACR ((CFG_SYS_CACHE_ICACR | \
Angelo Dureghello67c4e482017-08-07 01:17:18 +020092 CF_CACR_DEC | CF_CACR_DDCM_P | \
93 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
94
Tom Rini6a5dccc2022-11-16 13:10:41 -050095#define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \
96 CFG_SYS_INIT_RAM_SIZE - 12)
Angelo Dureghello67c4e482017-08-07 01:17:18 +020097
Angelo Dureghello67c4e482017-08-07 01:17:18 +020098#endif /* __STMARK2_CONFIG_H */