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Peng Fana181afe2019-09-16 03:09:55 +00001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2018 NXP
4 */
5
6#ifndef __IMX8MN_EVK_H
7#define __IMX8MN_EVK_H
8
9#include <linux/sizes.h>
Simon Glassfb64e362020-05-10 11:40:09 -060010#include <linux/stringify.h>
Peng Fana181afe2019-09-16 03:09:55 +000011#include <asm/arch/imx-regs.h>
12
Tom Rini6a5dccc2022-11-16 13:10:41 -050013#define CFG_SYS_UBOOT_BASE \
Peng Fana181afe2019-09-16 03:09:55 +000014 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
15
Andrey Zhizhikin9468aa12021-05-02 16:32:37 +020016#define BOOT_TARGET_DEVICES(func) \
17 func(MMC, mmc, 1) \
18 func(MMC, mmc, 2) \
19 func(DHCP, dhcp, na)
20
21#include <config_distro_bootcmd.h>
Andrey Zhizhikin9468aa12021-05-02 16:32:37 +020022
Peng Fana181afe2019-09-16 03:09:55 +000023/* Initial environment variables */
Heiko Thierye3d4dcd2022-02-24 21:07:14 +010024/* see include/configs/ti_armv7_common.h */
25#define ENV_MEM_LAYOUT_SETTINGS \
26 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
27 "kernel_addr_r=0x42000000\0" \
28 "fdt_addr_r=0x48000000\0" \
29 "fdtoverlay_addr_r=0x49000000\0" \
30 "ramdisk_addr_r=0x48080000\0" \
31 "initrd_addr=0x48080000\0" \
32 "scriptaddr=0x40000000\0" \
33 "pxefile_addr_r=0x40100000\0"
34
Tom Rinic9edebe2022-12-04 10:03:50 -050035#define CFG_EXTRA_ENV_SETTINGS \
Fabio Estevam3b483dd2021-03-04 08:07:16 -030036 "image=Image\0" \
Andrey Zhizhikin9468aa12021-05-02 16:32:37 +020037 BOOTENV \
Fabio Estevam21b135a2019-12-11 14:31:03 -030038 "console=ttymxc1,115200\0" \
Fabio Estevam3b483dd2021-03-04 08:07:16 -030039 "boot_fit=no\0" \
Andrey Zhizhikin9468aa12021-05-02 16:32:37 +020040 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
Grygorii Tertychnyi4d7cbe52020-08-21 15:39:43 +020041 "bootm_size=0x10000000\0" \
Tom Rinib113bca2021-12-11 14:55:52 -050042 "mmcpart=1\0" \
Peng Fanbb4bb582022-04-15 12:23:41 +080043 "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
Heiko Thierye3d4dcd2022-02-24 21:07:14 +010044 ENV_MEM_LAYOUT_SETTINGS
Peng Fana181afe2019-09-16 03:09:55 +000045
46/* Link Definitions */
Peng Fana181afe2019-09-16 03:09:55 +000047
Tom Rini6a5dccc2022-11-16 13:10:41 -050048#define CFG_SYS_INIT_RAM_ADDR 0x40000000
49#define CFG_SYS_INIT_RAM_SIZE 0x200000
Peng Fana181afe2019-09-16 03:09:55 +000050
Peng Fana181afe2019-09-16 03:09:55 +000051
Tom Rinibb4dd962022-11-16 13:10:37 -050052#define CFG_SYS_SDRAM_BASE 0x40000000
Peng Fana181afe2019-09-16 03:09:55 +000053#define PHYS_SDRAM 0x40000000
54#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
55
Peng Fana181afe2019-09-16 03:09:55 +000056#endif