blob: ab3c94e51275764df2e8b965329de604cc3d32e7 [file] [log] [blame]
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +05301/**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
Kishon Vijay Abraham Id1e431a2015-02-23 18:39:52 +05304 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +05305 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
Kishon Vijay Abraham Id1e431a2015-02-23 18:39:52 +05309 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
10 * to uboot.
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +053011 *
Kishon Vijay Abraham Id1e431a2015-02-23 18:39:52 +053012 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +053013 *
Kishon Vijay Abraham Id1e431a2015-02-23 18:39:52 +053014 * SPDX-License-Identifier: GPL-2.0
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +053015 */
16
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +053017#include <common.h>
18#include <malloc.h>
Kishon Vijay Abraham Ibfbf05d2015-02-23 18:40:04 +053019#include <dwc3-uboot.h>
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +053020#include <asm/dma-mapping.h>
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +053021#include <linux/ioport.h>
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +053022
23#include <linux/usb/ch9.h>
24#include <linux/usb/gadget.h>
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +053025
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +053026#include "core.h"
27#include "gadget.h"
28#include "io.h"
29
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +053030#include "linux-compat.h"
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +053031
Kishon Vijay Abraham Idc5c6532015-02-23 18:40:05 +053032static LIST_HEAD(dwc3_list);
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +053033/* -------------------------------------------------------------------------- */
34
Joonyoung Shimbf35c602015-03-03 17:32:09 +010035static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +053036{
37 u32 reg;
38
39 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
40 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
41 reg |= DWC3_GCTL_PRTCAPDIR(mode);
42 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
43}
44
45/**
46 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
47 * @dwc: pointer to our context structure
48 */
49static int dwc3_core_soft_reset(struct dwc3 *dwc)
50{
51 u32 reg;
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +053052
53 /* Before Resetting PHY, put Core in Reset */
54 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
55 reg |= DWC3_GCTL_CORESOFTRESET;
56 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
57
58 /* Assert USB3 PHY reset */
59 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
60 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
61 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
62
63 /* Assert USB2 PHY reset */
64 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
65 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
66 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
67
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +053068 mdelay(100);
69
70 /* Clear USB3 PHY reset */
71 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
72 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
73 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
74
75 /* Clear USB2 PHY reset */
76 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
77 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
78 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
79
80 mdelay(100);
81
82 /* After PHYs are stable we can take Core out of reset state */
83 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
84 reg &= ~DWC3_GCTL_CORESOFTRESET;
85 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
86
87 return 0;
88}
89
90/**
91 * dwc3_free_one_event_buffer - Frees one event buffer
92 * @dwc: Pointer to our controller context structure
93 * @evt: Pointer to event buffer to be freed
94 */
95static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
96 struct dwc3_event_buffer *evt)
97{
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +053098 dma_free_coherent(evt->buf);
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +053099}
100
101/**
102 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
103 * @dwc: Pointer to our controller context structure
104 * @length: size of the event buffer
105 *
106 * Returns a pointer to the allocated event buffer structure on success
107 * otherwise ERR_PTR(errno).
108 */
109static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
110 unsigned length)
111{
112 struct dwc3_event_buffer *evt;
113
114 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
115 if (!evt)
116 return ERR_PTR(-ENOMEM);
117
118 evt->dwc = dwc;
119 evt->length = length;
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +0530120 evt->buf = dma_alloc_coherent(length,
121 (unsigned long *)&evt->dma);
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530122 if (!evt->buf)
123 return ERR_PTR(-ENOMEM);
124
125 return evt;
126}
127
128/**
129 * dwc3_free_event_buffers - frees all allocated event buffers
130 * @dwc: Pointer to our controller context structure
131 */
132static void dwc3_free_event_buffers(struct dwc3 *dwc)
133{
134 struct dwc3_event_buffer *evt;
135 int i;
136
137 for (i = 0; i < dwc->num_event_buffers; i++) {
138 evt = dwc->ev_buffs[i];
139 if (evt)
140 dwc3_free_one_event_buffer(dwc, evt);
141 }
142}
143
144/**
145 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
146 * @dwc: pointer to our controller context structure
147 * @length: size of event buffer
148 *
149 * Returns 0 on success otherwise negative errno. In the error case, dwc
150 * may contain some buffers allocated but not all which were requested.
151 */
152static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
153{
154 int num;
155 int i;
156
157 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
158 dwc->num_event_buffers = num;
159
Kishon Vijay Abraham Ic7bdfe32015-02-23 18:40:13 +0530160 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
161 sizeof(*dwc->ev_buffs) * num);
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530162 if (!dwc->ev_buffs)
163 return -ENOMEM;
164
165 for (i = 0; i < num; i++) {
166 struct dwc3_event_buffer *evt;
167
168 evt = dwc3_alloc_one_event_buffer(dwc, length);
169 if (IS_ERR(evt)) {
170 dev_err(dwc->dev, "can't allocate event buffer\n");
171 return PTR_ERR(evt);
172 }
173 dwc->ev_buffs[i] = evt;
174 }
175
176 return 0;
177}
178
179/**
180 * dwc3_event_buffers_setup - setup our allocated event buffers
181 * @dwc: pointer to our controller context structure
182 *
183 * Returns 0 on success otherwise negative errno.
184 */
185static int dwc3_event_buffers_setup(struct dwc3 *dwc)
186{
187 struct dwc3_event_buffer *evt;
188 int n;
189
190 for (n = 0; n < dwc->num_event_buffers; n++) {
191 evt = dwc->ev_buffs[n];
192 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
193 evt->buf, (unsigned long long) evt->dma,
194 evt->length);
195
196 evt->lpos = 0;
197
198 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
199 lower_32_bits(evt->dma));
200 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
201 upper_32_bits(evt->dma));
202 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
203 DWC3_GEVNTSIZ_SIZE(evt->length));
204 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
205 }
206
207 return 0;
208}
209
210static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
211{
212 struct dwc3_event_buffer *evt;
213 int n;
214
215 for (n = 0; n < dwc->num_event_buffers; n++) {
216 evt = dwc->ev_buffs[n];
217
218 evt->lpos = 0;
219
220 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
221 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
222 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
223 | DWC3_GEVNTSIZ_SIZE(0));
224 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
225 }
226}
227
228static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
229{
230 if (!dwc->has_hibernation)
231 return 0;
232
233 if (!dwc->nr_scratch)
234 return 0;
235
236 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
237 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
238 if (!dwc->scratchbuf)
239 return -ENOMEM;
240
241 return 0;
242}
243
244static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
245{
246 dma_addr_t scratch_addr;
247 u32 param;
248 int ret;
249
250 if (!dwc->has_hibernation)
251 return 0;
252
253 if (!dwc->nr_scratch)
254 return 0;
255
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +0530256 scratch_addr = dma_map_single(dwc->scratchbuf,
257 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
258 DMA_BIDIRECTIONAL);
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530259 if (dma_mapping_error(dwc->dev, scratch_addr)) {
260 dev_err(dwc->dev, "failed to map scratch buffer\n");
261 ret = -EFAULT;
262 goto err0;
263 }
264
265 dwc->scratch_addr = scratch_addr;
266
267 param = lower_32_bits(scratch_addr);
268
269 ret = dwc3_send_gadget_generic_command(dwc,
270 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
271 if (ret < 0)
272 goto err1;
273
274 param = upper_32_bits(scratch_addr);
275
276 ret = dwc3_send_gadget_generic_command(dwc,
277 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
278 if (ret < 0)
279 goto err1;
280
281 return 0;
282
283err1:
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +0530284 dma_unmap_single((void *)dwc->scratch_addr, dwc->nr_scratch *
285 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530286
287err0:
288 return ret;
289}
290
291static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
292{
293 if (!dwc->has_hibernation)
294 return;
295
296 if (!dwc->nr_scratch)
297 return;
298
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +0530299 dma_unmap_single((void *)dwc->scratch_addr, dwc->nr_scratch *
300 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530301 kfree(dwc->scratchbuf);
302}
303
304static void dwc3_core_num_eps(struct dwc3 *dwc)
305{
306 struct dwc3_hwparams *parms = &dwc->hwparams;
307
308 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
309 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
310
311 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
312 dwc->num_in_eps, dwc->num_out_eps);
313}
314
315static void dwc3_cache_hwparams(struct dwc3 *dwc)
316{
317 struct dwc3_hwparams *parms = &dwc->hwparams;
318
319 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
320 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
321 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
322 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
323 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
324 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
325 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
326 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
327 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
328}
329
330/**
331 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
332 * @dwc: Pointer to our controller context structure
333 */
334static void dwc3_phy_setup(struct dwc3 *dwc)
335{
336 u32 reg;
337
338 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
339
340 /*
341 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
342 * to '0' during coreConsultant configuration. So default value
343 * will be '0' when the core is reset. Application needs to set it
344 * to '1' after the core initialization is completed.
345 */
346 if (dwc->revision > DWC3_REVISION_194A)
347 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
348
349 if (dwc->u2ss_inp3_quirk)
350 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
351
352 if (dwc->req_p1p2p3_quirk)
353 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
354
355 if (dwc->del_p1p2p3_quirk)
356 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
357
358 if (dwc->del_phy_power_chg_quirk)
359 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
360
361 if (dwc->lfps_filter_quirk)
362 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
363
364 if (dwc->rx_detect_poll_quirk)
365 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
366
367 if (dwc->tx_de_emphasis_quirk)
368 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
369
370 if (dwc->dis_u3_susphy_quirk)
371 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
372
373 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
374
375 mdelay(100);
376
377 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
378
379 /*
380 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
381 * '0' during coreConsultant configuration. So default value will
382 * be '0' when the core is reset. Application needs to set it to
383 * '1' after the core initialization is completed.
384 */
385 if (dwc->revision > DWC3_REVISION_194A)
386 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
387
388 if (dwc->dis_u2_susphy_quirk)
389 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
390
391 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
392
393 mdelay(100);
394}
395
396/**
397 * dwc3_core_init - Low-level initialization of DWC3 Core
398 * @dwc: Pointer to our controller context structure
399 *
400 * Returns 0 on success otherwise negative errno.
401 */
402static int dwc3_core_init(struct dwc3 *dwc)
403{
404 unsigned long timeout;
405 u32 hwparams4 = dwc->hwparams.hwparams4;
406 u32 reg;
407 int ret;
408
409 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
410 /* This should read as U3 followed by revision number */
411 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
412 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
413 ret = -ENODEV;
414 goto err0;
415 }
416 dwc->revision = reg;
417
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530418 /* Handle USB2.0-only core configuration */
419 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
420 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
421 if (dwc->maximum_speed == USB_SPEED_SUPER)
422 dwc->maximum_speed = USB_SPEED_HIGH;
423 }
424
425 /* issue device SoftReset too */
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +0530426 timeout = 5000;
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530427 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +0530428 while (timeout--) {
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530429 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
430 if (!(reg & DWC3_DCTL_CSFTRST))
431 break;
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +0530432 };
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530433
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +0530434 if (!timeout) {
435 dev_err(dwc->dev, "Reset Timed Out\n");
436 ret = -ETIMEDOUT;
437 goto err0;
438 }
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530439
440 ret = dwc3_core_soft_reset(dwc);
441 if (ret)
442 goto err0;
443
444 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
445 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
446
447 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
448 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
449 /**
450 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
451 * issue which would cause xHCI compliance tests to fail.
452 *
453 * Because of that we cannot enable clock gating on such
454 * configurations.
455 *
456 * Refers to:
457 *
458 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
459 * SOF/ITP Mode Used
460 */
461 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
462 dwc->dr_mode == USB_DR_MODE_OTG) &&
463 (dwc->revision >= DWC3_REVISION_210A &&
464 dwc->revision <= DWC3_REVISION_250A))
465 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
466 else
467 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
468 break;
469 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
470 /* enable hibernation here */
471 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
472
473 /*
474 * REVISIT Enabling this bit so that host-mode hibernation
475 * will work. Device-mode hibernation is not yet implemented.
476 */
477 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
478 break;
479 default:
480 dev_dbg(dwc->dev, "No power optimization available\n");
481 }
482
483 /* check if current dwc3 is on simulation board */
484 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
485 dev_dbg(dwc->dev, "it is on FPGA board\n");
486 dwc->is_fpga = true;
487 }
488
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +0530489 if(dwc->disable_scramble_quirk && !dwc->is_fpga)
490 WARN(true,
491 "disable_scramble cannot be used on non-FPGA builds\n");
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530492
493 if (dwc->disable_scramble_quirk && dwc->is_fpga)
494 reg |= DWC3_GCTL_DISSCRAMBLE;
495 else
496 reg &= ~DWC3_GCTL_DISSCRAMBLE;
497
498 if (dwc->u2exit_lfps_quirk)
499 reg |= DWC3_GCTL_U2EXIT_LFPS;
500
501 /*
502 * WORKAROUND: DWC3 revisions <1.90a have a bug
503 * where the device can fail to connect at SuperSpeed
504 * and falls back to high-speed mode which causes
505 * the device to enter a Connect/Disconnect loop
506 */
507 if (dwc->revision < DWC3_REVISION_190A)
508 reg |= DWC3_GCTL_U2RSTECN;
509
510 dwc3_core_num_eps(dwc);
511
512 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
513
514 dwc3_phy_setup(dwc);
515
516 ret = dwc3_alloc_scratch_buffers(dwc);
517 if (ret)
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +0530518 goto err0;
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530519
520 ret = dwc3_setup_scratch_buffers(dwc);
521 if (ret)
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +0530522 goto err1;
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530523
524 return 0;
525
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530526err1:
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +0530527 dwc3_free_scratch_buffers(dwc);
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530528
529err0:
530 return ret;
531}
532
533static void dwc3_core_exit(struct dwc3 *dwc)
534{
535 dwc3_free_scratch_buffers(dwc);
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530536}
537
538static int dwc3_core_init_mode(struct dwc3 *dwc)
539{
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530540 int ret;
541
542 switch (dwc->dr_mode) {
543 case USB_DR_MODE_PERIPHERAL:
544 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
545 ret = dwc3_gadget_init(dwc);
546 if (ret) {
547 dev_err(dev, "failed to initialize gadget\n");
548 return ret;
549 }
550 break;
551 case USB_DR_MODE_HOST:
552 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
553 ret = dwc3_host_init(dwc);
554 if (ret) {
555 dev_err(dev, "failed to initialize host\n");
556 return ret;
557 }
558 break;
559 case USB_DR_MODE_OTG:
560 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
561 ret = dwc3_host_init(dwc);
562 if (ret) {
563 dev_err(dev, "failed to initialize host\n");
564 return ret;
565 }
566
567 ret = dwc3_gadget_init(dwc);
568 if (ret) {
569 dev_err(dev, "failed to initialize gadget\n");
570 return ret;
571 }
572 break;
573 default:
574 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
575 return -EINVAL;
576 }
577
578 return 0;
579}
580
581static void dwc3_core_exit_mode(struct dwc3 *dwc)
582{
583 switch (dwc->dr_mode) {
584 case USB_DR_MODE_PERIPHERAL:
585 dwc3_gadget_exit(dwc);
586 break;
587 case USB_DR_MODE_HOST:
588 dwc3_host_exit(dwc);
589 break;
590 case USB_DR_MODE_OTG:
591 dwc3_host_exit(dwc);
592 dwc3_gadget_exit(dwc);
593 break;
594 default:
595 /* do nothing */
596 break;
597 }
598}
599
600#define DWC3_ALIGN_MASK (16 - 1)
601
Kishon Vijay Abraham Ibfbf05d2015-02-23 18:40:04 +0530602/**
603 * dwc3_uboot_init - dwc3 core uboot initialization code
604 * @dwc3_dev: struct dwc3_device containing initialization data
605 *
606 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
607 * kernel driver). Pointer to dwc3_device should be passed containing
608 * base address and other initialization data. Returns '0' on success and
609 * a negative value on failure.
610 *
611 * Generally called from board_usb_init() implemented in board file.
612 */
613int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530614{
Kishon Vijay Abraham Idc5c6532015-02-23 18:40:05 +0530615 struct dwc3 *dwc;
Kishon Vijay Abraham Ibfbf05d2015-02-23 18:40:04 +0530616 struct device *dev;
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530617 u8 lpm_nyet_threshold;
618 u8 tx_de_emphasis;
619 u8 hird_threshold;
620
621 int ret;
622
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530623 void *mem;
624
625 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
626 if (!mem)
627 return -ENOMEM;
628
629 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
630 dwc->mem = mem;
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530631
Kishon Vijay Abraham Ibfbf05d2015-02-23 18:40:04 +0530632 dwc->regs = (int *)(dwc3_dev->base + DWC3_GLOBALS_REGS_START);
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530633
634 /* default to highest possible threshold */
635 lpm_nyet_threshold = 0xff;
636
637 /* default to -3.5dB de-emphasis */
638 tx_de_emphasis = 1;
639
640 /*
641 * default to assert utmi_sleep_n and use maximum allowed HIRD
642 * threshold value of 0b1100
643 */
644 hird_threshold = 12;
645
Kishon Vijay Abraham Ibfbf05d2015-02-23 18:40:04 +0530646 dwc->maximum_speed = dwc3_dev->maximum_speed;
647 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
648 if (dwc3_dev->lpm_nyet_threshold)
649 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
650 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
651 if (dwc3_dev->hird_threshold)
652 hird_threshold = dwc3_dev->hird_threshold;
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530653
Kishon Vijay Abraham Ibfbf05d2015-02-23 18:40:04 +0530654 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
655 dwc->dr_mode = dwc3_dev->dr_mode;
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530656
Kishon Vijay Abraham Ibfbf05d2015-02-23 18:40:04 +0530657 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
658 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
659 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
660 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
661 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
662 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
663 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
664 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
665 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
666 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530667
Kishon Vijay Abraham Ibfbf05d2015-02-23 18:40:04 +0530668 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
669 if (dwc3_dev->tx_de_emphasis)
670 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530671
672 /* default to superspeed if no maximum_speed passed */
673 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
674 dwc->maximum_speed = USB_SPEED_SUPER;
675
676 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
677 dwc->tx_de_emphasis = tx_de_emphasis;
678
679 dwc->hird_threshold = hird_threshold
680 | (dwc->is_utmi_l1_suspend << 4);
681
Kishon Vijay Abraham Idc5c6532015-02-23 18:40:05 +0530682 dwc->index = dwc3_dev->index;
683
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530684 dwc3_cache_hwparams(dwc);
685
686 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
687 if (ret) {
688 dev_err(dwc->dev, "failed to allocate event buffers\n");
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +0530689 return -ENOMEM;
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530690 }
691
692 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
693 dwc->dr_mode = USB_DR_MODE_HOST;
694 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
695 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
696
697 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
698 dwc->dr_mode = USB_DR_MODE_OTG;
699
700 ret = dwc3_core_init(dwc);
701 if (ret) {
702 dev_err(dev, "failed to initialize core\n");
703 goto err0;
704 }
705
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530706 ret = dwc3_event_buffers_setup(dwc);
707 if (ret) {
708 dev_err(dwc->dev, "failed to setup event buffers\n");
Kishon Vijay Abraham I99030d72015-02-23 18:40:02 +0530709 goto err1;
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530710 }
711
712 ret = dwc3_core_init_mode(dwc);
713 if (ret)
714 goto err2;
715
Kishon Vijay Abraham Idc5c6532015-02-23 18:40:05 +0530716 list_add_tail(&dwc->list, &dwc3_list);
717
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530718 return 0;
719
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530720err2:
721 dwc3_event_buffers_cleanup(dwc);
722
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530723err1:
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530724 dwc3_core_exit(dwc);
725
726err0:
727 dwc3_free_event_buffers(dwc);
728
729 return ret;
730}
731
Kishon Vijay Abraham Ibfbf05d2015-02-23 18:40:04 +0530732/**
733 * dwc3_uboot_exit - dwc3 core uboot cleanup code
734 * @index: index of this controller
735 *
736 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
Kishon Vijay Abraham Idc5c6532015-02-23 18:40:05 +0530737 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
738 * should be passed and should match with the index passed in
739 * dwc3_device during init.
Kishon Vijay Abraham Ibfbf05d2015-02-23 18:40:04 +0530740 *
741 * Generally called from board file.
742 */
Kishon Vijay Abraham Idc5c6532015-02-23 18:40:05 +0530743void dwc3_uboot_exit(int index)
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530744{
Kishon Vijay Abraham Idc5c6532015-02-23 18:40:05 +0530745 struct dwc3 *dwc;
746
747 list_for_each_entry(dwc, &dwc3_list, list) {
748 if (dwc->index != index)
749 continue;
750
751 dwc3_core_exit_mode(dwc);
752 dwc3_event_buffers_cleanup(dwc);
753 dwc3_free_event_buffers(dwc);
754 dwc3_core_exit(dwc);
755 list_del(&dwc->list);
756 kfree(dwc->mem);
757 break;
758 }
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530759}
760
Kishon Vijay Abraham I1cee7b12015-02-23 18:40:06 +0530761/**
762 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
763 * @index: index of this controller
764 *
765 * Invokes dwc3 gadget interrupts.
766 *
767 * Generally called from board file.
768 */
769void dwc3_uboot_handle_interrupt(int index)
770{
771 struct dwc3 *dwc = NULL;
772
773 list_for_each_entry(dwc, &dwc3_list, list) {
774 if (dwc->index != index)
775 continue;
776
777 dwc3_gadget_uboot_handle_interrupt(dwc);
778 break;
779 }
780}
781
Kishon Vijay Abraham I1530fe32015-02-23 18:39:50 +0530782MODULE_ALIAS("platform:dwc3");
783MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
784MODULE_LICENSE("GPL v2");
785MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");