wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * board/config.h - configuration options, board specific |
| 10 | */ |
| 11 | |
| 12 | #ifndef __CONFIG_H |
| 13 | #define __CONFIG_H |
| 14 | |
| 15 | /* |
| 16 | * High Level Configuration Options |
| 17 | * (easy to change) |
| 18 | */ |
| 19 | |
| 20 | #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ |
| 21 | #define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */ |
| 22 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 23 | #define CONFIG_SYS_TEXT_BASE 0xFF000000 |
| 24 | |
Peter Tyser | d3d9a50 | 2009-09-16 22:03:08 -0500 | [diff] [blame] | 25 | #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ |
| 26 | |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 27 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
| 28 | #undef CONFIG_8xx_CONS_SMC2 |
| 29 | #undef CONFIG_8xx_CONS_NONE |
| 30 | #define CONFIG_BAUDRATE 115200 |
| 31 | #if 0 |
| 32 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
| 33 | #else |
| 34 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 35 | #endif |
| 36 | |
| 37 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
| 38 | |
| 39 | #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ |
| 40 | |
| 41 | #define CONFIG_BOOTARGS "root=/dev/nfs rw " \ |
| 42 | "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ |
| 43 | "nfsaddrs=10.0.0.99:10.0.0.2" |
| 44 | |
| 45 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 46 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 47 | |
| 48 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 49 | |
Jon Loeliger | d866df3 | 2007-07-08 15:02:44 -0500 | [diff] [blame] | 50 | |
| 51 | /* |
| 52 | * Command line configuration. |
| 53 | */ |
| 54 | #include <config_cmd_default.h> |
| 55 | |
| 56 | #define CONFIG_CMD_IDE |
| 57 | |
Mike Frysinger | 78dcaf4 | 2009-01-28 19:08:14 -0500 | [diff] [blame] | 58 | #undef CONFIG_CMD_SAVEENV |
Jon Loeliger | d866df3 | 2007-07-08 15:02:44 -0500 | [diff] [blame] | 59 | #undef CONFIG_CMD_FLASH |
| 60 | |
| 61 | |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 62 | #define CONFIG_MAC_PARTITION |
| 63 | #define CONFIG_DOS_PARTITION |
| 64 | |
Jon Loeliger | 7846bb2 | 2007-07-09 21:31:24 -0500 | [diff] [blame] | 65 | /* |
| 66 | * BOOTP options |
| 67 | */ |
| 68 | #define CONFIG_BOOTP_SUBNETMASK |
| 69 | #define CONFIG_BOOTP_GATEWAY |
| 70 | #define CONFIG_BOOTP_HOSTNAME |
| 71 | #define CONFIG_BOOTP_BOOTPATH |
| 72 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 73 | |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 74 | |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 75 | /*----------------------------------------------------------------------*/ |
| 76 | #define CONFIG_ETHADDR 00:D0:93:00:01:CB |
| 77 | #define CONFIG_IPADDR 10.0.0.98 |
| 78 | #define CONFIG_SERVERIP 10.0.0.1 |
| 79 | #undef CONFIG_BOOTCOMMAND |
wdenk | ef5fe75 | 2003-03-12 10:41:04 +0000 | [diff] [blame] | 80 | #define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000" |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 81 | /*----------------------------------------------------------------------*/ |
| 82 | |
| 83 | /* |
| 84 | * Miscellaneous configurable options |
| 85 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 86 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 87 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
Jon Loeliger | d866df3 | 2007-07-08 15:02:44 -0500 | [diff] [blame] | 88 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 89 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 90 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 91 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 92 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 93 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 94 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 95 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 96 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 97 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
| 98 | #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 99 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 100 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 101 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 102 | #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 103 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 104 | #define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 105 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 106 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 107 | |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 108 | /* |
| 109 | * Low Level Configuration Settings |
| 110 | * (address mappings, register initial values, etc.) |
| 111 | * You should know what you are doing if you make changes here. |
| 112 | */ |
| 113 | /*----------------------------------------------------------------------- |
| 114 | * Internal Memory Mapped Register |
| 115 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 116 | #define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 117 | |
| 118 | /*----------------------------------------------------------------------- |
| 119 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 120 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 121 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 122 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 123 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 124 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 125 | |
| 126 | /*----------------------------------------------------------------------- |
| 127 | * Start addresses for the final memory configuration |
| 128 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 129 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 130 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 131 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 132 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 133 | #ifdef DEBUG |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 134 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 135 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 136 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 137 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 138 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 139 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 140 | |
| 141 | /* |
| 142 | * For booting Linux, the board info and command line data |
| 143 | * have to be in the first 8 MB of memory, since this is |
| 144 | * the maximum mapped by the Linux kernel during initialization. |
| 145 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 146 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 147 | /*----------------------------------------------------------------------- |
| 148 | * FLASH organization |
| 149 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 150 | #define CONFIG_SYS_MAX_FLASH_BANKS 0 /* max number of memory banks */ |
| 151 | #define CONFIG_SYS_MAX_FLASH_SECT 0 /* max number of sectors on one chip */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 152 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 153 | #define CONFIG_SYS_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */ |
| 154 | #define CONFIG_SYS_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 155 | |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 156 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 157 | #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
| 158 | #define CONFIG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 159 | /*----------------------------------------------------------------------- |
| 160 | * Cache Configuration |
| 161 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 162 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
Jon Loeliger | d866df3 | 2007-07-08 15:02:44 -0500 | [diff] [blame] | 163 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 164 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 165 | #endif |
| 166 | |
| 167 | /*----------------------------------------------------------------------- |
| 168 | * SYPCR - System Protection Control 11-9 |
| 169 | * SYPCR can only be written once after reset! |
| 170 | *----------------------------------------------------------------------- |
| 171 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
| 172 | */ |
| 173 | #if defined(CONFIG_WATCHDOG) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 174 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 175 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
| 176 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 177 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 178 | #endif |
| 179 | |
| 180 | /*----------------------------------------------------------------------- |
| 181 | * SIUMCR - SIU Module Configuration 11-6 |
| 182 | *----------------------------------------------------------------------- |
| 183 | * PCMCIA config., multi-function pin tri-state |
| 184 | */ |
| 185 | /* 0x00000040 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 186 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 187 | |
| 188 | /*----------------------------------------------------------------------- |
| 189 | * TBSCR - Time Base Status and Control 11-26 |
| 190 | *----------------------------------------------------------------------- |
| 191 | * Clear Reference Interrupt Status, Timebase freezing enabled |
| 192 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 193 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 194 | |
| 195 | /*----------------------------------------------------------------------- |
| 196 | * PISCR - Periodic Interrupt Status and Control 11-31 |
| 197 | *----------------------------------------------------------------------- |
| 198 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
| 199 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 200 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 201 | |
| 202 | /*----------------------------------------------------------------------- |
| 203 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
| 204 | *----------------------------------------------------------------------- |
| 205 | * Reset PLL lock status sticky bit, timer expired status bit and timer |
| 206 | * interrupt status bit, set PLL multiplication factor ! |
| 207 | */ |
| 208 | /* 0x00b0c0c0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 209 | #define CONFIG_SYS_PLPRCR \ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 210 | ( (11 << PLPRCR_MF_SHIFT) | \ |
| 211 | PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ |
| 212 | /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ |
| 213 | PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ |
| 214 | ) |
| 215 | |
| 216 | /*----------------------------------------------------------------------- |
| 217 | * SCCR - System Clock and reset Control Register 15-27 |
| 218 | *----------------------------------------------------------------------- |
| 219 | * Set clock output, timebase and RTC source and divider, |
| 220 | * power management and some other internal clocks |
| 221 | */ |
| 222 | #define SCCR_MASK SCCR_EBDF11 |
| 223 | /* 0x01800014 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 224 | #define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 225 | SCCR_RTDIV | SCCR_RTSEL | \ |
| 226 | /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ |
| 227 | SCCR_EBDF00 | SCCR_DFSYNC00 | \ |
| 228 | SCCR_DFBRG00 | SCCR_DFNL000 | \ |
| 229 | SCCR_DFNH000 | SCCR_DFLCD101 | \ |
| 230 | SCCR_DFALCD00) |
| 231 | |
| 232 | /*----------------------------------------------------------------------- |
| 233 | * RTCSC - Real-Time Clock Status and Control Register |
| 234 | *----------------------------------------------------------------------- |
| 235 | */ |
| 236 | /* 0x00C3 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 237 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 238 | |
| 239 | |
| 240 | /*----------------------------------------------------------------------- |
| 241 | * RCCR - RISC Controller Configuration Register |
| 242 | *----------------------------------------------------------------------- |
| 243 | */ |
| 244 | /* TIMEP=2 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 245 | #define CONFIG_SYS_RCCR 0x0200 |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 246 | |
| 247 | /*----------------------------------------------------------------------- |
| 248 | * RMDS - RISC Microcode Development Support Control Register |
| 249 | *----------------------------------------------------------------------- |
| 250 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 251 | #define CONFIG_SYS_RMDS 0 |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 252 | |
| 253 | /*----------------------------------------------------------------------- |
| 254 | * SDSR - SDMA Status Register |
| 255 | *----------------------------------------------------------------------- |
| 256 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 257 | #define CONFIG_SYS_SDSR ((u_char)0x83) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 258 | |
| 259 | /*----------------------------------------------------------------------- |
| 260 | * SDMR - SDMA Mask Register |
| 261 | *----------------------------------------------------------------------- |
| 262 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 263 | #define CONFIG_SYS_SDMR ((u_char)0x00) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 264 | |
| 265 | /*----------------------------------------------------------------------- |
| 266 | * |
| 267 | * Interrupt Levels |
| 268 | *----------------------------------------------------------------------- |
| 269 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 270 | #define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 271 | |
| 272 | /*----------------------------------------------------------------------- |
| 273 | * PCMCIA stuff |
| 274 | *----------------------------------------------------------------------- |
| 275 | * |
| 276 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 277 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
| 278 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
| 279 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
| 280 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
| 281 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
| 282 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
| 283 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
| 284 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 285 | |
| 286 | /*----------------------------------------------------------------------- |
| 287 | * IDE/ATA stuff |
| 288 | *----------------------------------------------------------------------- |
| 289 | */ |
Pavel Herrmann | 2c13c4a | 2012-10-09 07:01:56 +0000 | [diff] [blame] | 290 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
| 291 | #define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 292 | #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ |
| 293 | #define CONFIG_IDE_LED 1 /* LED for ide supported */ |
| 294 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
| 295 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 296 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
| 297 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 298 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 299 | #define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000 |
| 300 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
| 301 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00 |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 302 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 303 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
| 304 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ |
| 305 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 306 | |
| 307 | /*----------------------------------------------------------------------- |
| 308 | * |
| 309 | *----------------------------------------------------------------------- |
| 310 | * |
| 311 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 312 | #define CONFIG_SYS_DER 0 |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 313 | |
| 314 | /* |
| 315 | * Init Memory Controller: |
| 316 | * |
| 317 | * BR0/1 and OR0/1 (FLASH) |
| 318 | */ |
| 319 | |
| 320 | #define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ |
| 321 | #define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */ |
| 322 | |
| 323 | /* used to re-map FLASH both when starting from SRAM or FLASH: |
| 324 | * restrict access enough to keep SRAM working (if any) |
| 325 | * but not too much to meddle with FLASH accesses |
| 326 | */ |
| 327 | /* EPROMs are 512kb */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 328 | #define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ |
| 329 | #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 330 | |
| 331 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 332 | #define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 333 | OR_SCY_5_CLK | OR_EHTR) |
| 334 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 335 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
| 336 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 337 | /* 16 bit, bank valid */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 338 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 339 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 340 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
| 341 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 342 | /* 16 bit, bank valid */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 343 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 344 | |
| 345 | /* |
| 346 | * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC) |
| 347 | * |
| 348 | */ |
| 349 | #define SRAM_BASE 0xFE200000 /* SRAM bank */ |
| 350 | #define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */ |
| 351 | |
| 352 | #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ |
| 353 | #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ |
| 354 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ |
| 355 | |
| 356 | #define PER8_BASE 0xFE000000 /* PER8 bank */ |
| 357 | #define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */ |
| 358 | |
| 359 | #define SHARC_BASE 0xFE400000 /* SHARC bank */ |
| 360 | #define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */ |
| 361 | |
| 362 | /* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
| 363 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 364 | #define CONFIG_SYS_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */ |
| 365 | #define CONFIG_SYS_OR2 (SRAM_OR_AM | CONFIG_SYS_OR_TIMING_SRAM ) |
| 366 | #define CONFIG_SYS_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 367 | |
| 368 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
| 369 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 370 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */ |
| 371 | #define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
| 372 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 373 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 374 | #define CONFIG_SYS_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */ |
| 375 | #define CONFIG_SYS_OR4 (PER8_OR_AM | CONFIG_SYS_OR_TIMING_PER8 ) |
| 376 | #define CONFIG_SYS_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 377 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 378 | #define CONFIG_SYS_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */ |
| 379 | #define CONFIG_SYS_OR5 (SHARC_OR_AM | CONFIG_SYS_OR_TIMING_SHARC ) |
| 380 | #define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 381 | /* |
| 382 | * Memory Periodic Timer Prescaler |
| 383 | */ |
| 384 | |
| 385 | /* periodic timer for refresh */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 386 | #define CONFIG_SYS_MBMR_PTB 204 |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 387 | |
| 388 | /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 389 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
| 390 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 391 | |
| 392 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 393 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
| 394 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 395 | |
| 396 | /* |
| 397 | * MBMR settings for SDRAM |
| 398 | */ |
| 399 | |
| 400 | /* 8 column SDRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 401 | #define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ |
wdenk | 2bb1105 | 2003-07-17 23:16:40 +0000 | [diff] [blame] | 402 | MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ |
| 403 | MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 404 | |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 405 | #endif /* __CONFIG_H */ |