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wdenka7316b02005-05-12 22:48:09 +00001/*
2 * (C) Copyright 2005
3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenka7316b02005-05-12 22:48:09 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
21#define CONFIG_MPC8272_FAMILY 1
22#define CONFIG_IDS8247 1
23#define CPU_ID_STR "MPC8247"
Jon Loeligerf5ad3782005-07-23 10:37:35 -050024#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenka7316b02005-05-12 22:48:09 +000025
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020026#define CONFIG_SYS_TEXT_BASE 0xfff00000
27
wdenka7316b02005-05-12 22:48:09 +000028#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
29
30#define CONFIG_BOOTCOUNT_LIMIT
31
Wolfgang Denk1baed662008-03-03 12:16:44 +010032#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenka7316b02005-05-12 22:48:09 +000033
34#undef CONFIG_BOOTARGS
35
36#define CONFIG_EXTRA_ENV_SETTINGS \
37 "netdev=eth0\0" \
38 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010039 "nfsroot=${serverip}:${rootpath}\0" \
wdenka7316b02005-05-12 22:48:09 +000040 "ramargs=setenv bootargs root=/dev/ram rw " \
41 "console=ttyS0,115200\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010042 "addip=setenv bootargs ${bootargs} " \
43 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
44 ":${hostname}:${netdev}:off panic=1\0" \
wdenka7316b02005-05-12 22:48:09 +000045 "flash_nfs=run nfsargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010046 "bootm ${kernel_addr}\0" \
wdenka7316b02005-05-12 22:48:09 +000047 "flash_self=run ramargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010048 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
49 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenka7316b02005-05-12 22:48:09 +000050 "rootpath=/opt/eldk/ppc_82xx\0" \
51 "bootfile=/tftpboot/IDS8247/uImage\0" \
52 "kernel_addr=ff800000\0" \
53 "ramdisk_addr=ffa00000\0" \
54 ""
55#define CONFIG_BOOTCOMMAND "run flash_self"
56
57#define CONFIG_MISC_INIT_R 1
58
59/* enable I2C and select the hardware/software driver */
Heiko Schocher479a4cf2013-01-29 08:53:15 +010060#define CONFIG_SYS_I2C
61#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
62#define CONFIG_SYS_I2C_SOFT_SPEED 400000
63#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
wdenka7316b02005-05-12 22:48:09 +000064/*
65 * Software (bit-bang) I2C driver configuration
66 */
67
68#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */
69#define I2C_ACTIVE (iop->pdir |= 0x00000080)
70#define I2C_TRISTATE (iop->pdir &= ~0x00000080)
71#define I2C_READ ((iop->pdat & 0x00000080) != 0)
72#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \
73 else iop->pdat &= ~0x00000080
74#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \
75 else iop->pdat &= ~0x00000100
76#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
77
78#if 0
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
80#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
81#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
82#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenka7316b02005-05-12 22:48:09 +000083
84#define CONFIG_I2C_X
85#endif
86
87/*
88 * select serial console configuration
89 * use the extern UART for the console
90 */
91#define CONFIG_CONS_INDEX 1
92#define CONFIG_BAUDRATE 115200
93/*
94 * NS16550 Configuration
95 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_NS16550
97#define CONFIG_SYS_NS16550_SERIAL
wdenka7316b02005-05-12 22:48:09 +000098
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenka7316b02005-05-12 22:48:09 +0000100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#define CONFIG_SYS_NS16550_CLK 14745600
wdenka7316b02005-05-12 22:48:09 +0000102
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200103#define CONFIG_SYS_UART_BASE 0xE0000000
104#define CONFIG_SYS_UART_SIZE 0x10000
wdenka7316b02005-05-12 22:48:09 +0000105
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000)
wdenka7316b02005-05-12 22:48:09 +0000107
Sergej Stepanovfff10d42007-10-17 11:18:42 +0200108
109/* pass open firmware flat tree */
110#define CONFIG_OF_LIBFDT 1
111#define CONFIG_OF_BOARD_SETUP 1
112
Sergej Stepanovfff10d42007-10-17 11:18:42 +0200113#define OF_TBCLK (bd->bi_busfreq / 4)
114#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000"
115
116
wdenka7316b02005-05-12 22:48:09 +0000117/*
118 * select ethernet configuration
119 *
120 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
121 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
122 * for FCC)
123 *
124 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger2517d972007-07-09 17:15:49 -0500125 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenka7316b02005-05-12 22:48:09 +0000126 */
127#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
128#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
129#undef CONFIG_ETHER_NONE /* define if ether on something else */
Sergej Stepanovfff10d42007-10-17 11:18:42 +0200130#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
131#define CONFIG_ETHER_ON_FCC1
132#define FCC_ENET
wdenka7316b02005-05-12 22:48:09 +0000133
134/*
Sergej Stepanovfff10d42007-10-17 11:18:42 +0200135 * - Rx-CLK is CLK10
136 * - Tx-CLK is CLK9
wdenka7316b02005-05-12 22:48:09 +0000137 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
138 * - Enable Full Duplex in FSMR
139 */
Mike Frysinger109de972011-10-17 05:38:58 +0000140# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
141# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142# define CONFIG_SYS_CPMFCR_RAMTYPE 0
143# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenka7316b02005-05-12 22:48:09 +0000144
145
146/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
147#define CONFIG_8260_CLKIN 66666666 /* in Hz */
148
149#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenka7316b02005-05-12 22:48:09 +0000151
152#undef CONFIG_WATCHDOG /* watchdog disabled */
153
154#define CONFIG_TIMESTAMP /* Print image info with timestamp */
155
Jon Loeligerdf5f5442007-07-09 21:24:19 -0500156/*
157 * BOOTP options
158 */
159#define CONFIG_BOOTP_SUBNETMASK
160#define CONFIG_BOOTP_GATEWAY
161#define CONFIG_BOOTP_HOSTNAME
162#define CONFIG_BOOTP_BOOTPATH
163#define CONFIG_BOOTP_BOOTFILESIZE
wdenka7316b02005-05-12 22:48:09 +0000164
Sergej Stepanovfff10d42007-10-17 11:18:42 +0200165#define CONFIG_RTC_PCF8563
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166#define CONFIG_SYS_I2C_RTC_ADDR 0x51
wdenka7316b02005-05-12 22:48:09 +0000167
Jon Loeligerb1840de2007-07-08 13:46:18 -0500168/*
169 * Command line configuration.
170 */
171#include <config_cmd_default.h>
172
173#define CONFIG_CMD_DHCP
174#define CONFIG_CMD_NFS
175#define CONFIG_CMD_NAND
176#define CONFIG_CMD_I2C
177#define CONFIG_CMD_SNTP
178
wdenka7316b02005-05-12 22:48:09 +0000179
180/*
181 * Miscellaneous configurable options
182 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200183#define CONFIG_SYS_LONGHELP /* undef to save memory */
184#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerb1840de2007-07-08 13:46:18 -0500185#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200186#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenka7316b02005-05-12 22:48:09 +0000187#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200188#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenka7316b02005-05-12 22:48:09 +0000189#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
191#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
192#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenka7316b02005-05-12 22:48:09 +0000193
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200194#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
195#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenka7316b02005-05-12 22:48:09 +0000196
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenka7316b02005-05-12 22:48:09 +0000198
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenka7316b02005-05-12 22:48:09 +0000200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
wdenka7316b02005-05-12 22:48:09 +0000202
203/*
204 * For booting Linux, the board info and command line data
205 * have to be in the first 8 MB of memory, since this is
206 * the maximum mapped by the Linux kernel during initialization.
207 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenka7316b02005-05-12 22:48:09 +0000209
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200211#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 }
Stefan Roesefb9a7302010-08-31 10:00:10 +0200213#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenka7316b02005-05-12 22:48:09 +0000214/* What should the base address of the main FLASH be and how big is
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200215 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk
wdenka7316b02005-05-12 22:48:09 +0000216 * The main FLASH is whichever is connected to *CS0.
217 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#define CONFIG_SYS_FLASH0_BASE 0xFFF00000
219#define CONFIG_SYS_FLASH0_SIZE 8
wdenka7316b02005-05-12 22:48:09 +0000220
221/* Flash bank size (for preliminary settings)
222 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200223#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
wdenka7316b02005-05-12 22:48:09 +0000224
225/*-----------------------------------------------------------------------
226 * FLASH organization
227 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
wdenka7316b02005-05-12 22:48:09 +0000229
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200230#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
231#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenka7316b02005-05-12 22:48:09 +0000232
233/* Environment in flash */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200234#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200235#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200236#define CONFIG_ENV_SIZE 0x20000
237#define CONFIG_ENV_SECT_SIZE 0x20000
wdenka7316b02005-05-12 22:48:09 +0000238
239/*-----------------------------------------------------------------------
240 * NAND-FLASH stuff
241 *-----------------------------------------------------------------------
242 */
Jon Loeligerb1840de2007-07-08 13:46:18 -0500243#if defined(CONFIG_CMD_NAND)
wdenka7316b02005-05-12 22:48:09 +0000244
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200245#define CONFIG_SYS_NAND0_BASE 0xE1000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200246#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
wdenka7316b02005-05-12 22:48:09 +0000247
Jon Loeligerf5709d12007-07-10 09:02:57 -0500248#endif /* CONFIG_CMD_NAND */
wdenka7316b02005-05-12 22:48:09 +0000249
250/*-----------------------------------------------------------------------
251 * Hard Reset Configuration Words
252 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200253 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenka7316b02005-05-12 22:48:09 +0000254 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200255 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenka7316b02005-05-12 22:48:09 +0000256 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200257#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
wdenka7316b02005-05-12 22:48:09 +0000258
259/* no slaves so just fill with zeros */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200260#define CONFIG_SYS_HRCW_SLAVE1 0
261#define CONFIG_SYS_HRCW_SLAVE2 0
262#define CONFIG_SYS_HRCW_SLAVE3 0
263#define CONFIG_SYS_HRCW_SLAVE4 0
264#define CONFIG_SYS_HRCW_SLAVE5 0
265#define CONFIG_SYS_HRCW_SLAVE6 0
266#define CONFIG_SYS_HRCW_SLAVE7 0
wdenka7316b02005-05-12 22:48:09 +0000267
268/*-----------------------------------------------------------------------
269 * Internal Memory Mapped Register
270 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200271#define CONFIG_SYS_IMMR 0xF0000000
wdenka7316b02005-05-12 22:48:09 +0000272
273/*-----------------------------------------------------------------------
274 * Definitions for initial stack pointer and data area (in DPRAM)
275 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200276#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200277#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200278#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200279#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenka7316b02005-05-12 22:48:09 +0000280
281/*-----------------------------------------------------------------------
282 * Start addresses for the final memory configuration
283 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200284 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenka7316b02005-05-12 22:48:09 +0000285 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200286 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
wdenka7316b02005-05-12 22:48:09 +0000287 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200288#define CONFIG_SYS_SDRAM_BASE 0x00000000
289#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200290#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200291#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
292#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
wdenka7316b02005-05-12 22:48:09 +0000293
wdenka7316b02005-05-12 22:48:09 +0000294/*-----------------------------------------------------------------------
295 * Cache Configuration
296 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200297#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeligerb1840de2007-07-08 13:46:18 -0500298#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200299# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenka7316b02005-05-12 22:48:09 +0000300#endif
301
302/*-----------------------------------------------------------------------
303 * HIDx - Hardware Implementation-dependent Registers 2-11
304 *-----------------------------------------------------------------------
305 * HID0 also contains cache control - initially enable both caches and
306 * invalidate contents, then the final state leaves only the instruction
307 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
308 * but Soft reset does not.
309 *
310 * HID1 has only read-only information - nothing to set.
311 */
312
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200313#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
314#define CONFIG_SYS_HID0_FINAL 0
315#define CONFIG_SYS_HID2 0
wdenka7316b02005-05-12 22:48:09 +0000316
317/*-----------------------------------------------------------------------
318 * RMR - Reset Mode Register 5-5
319 *-----------------------------------------------------------------------
320 * turn on Checkstop Reset Enable
321 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200322#define CONFIG_SYS_RMR 0
wdenka7316b02005-05-12 22:48:09 +0000323
324/*-----------------------------------------------------------------------
325 * BCR - Bus Configuration 4-25
326 *-----------------------------------------------------------------------
327 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200328#define CONFIG_SYS_BCR 0
wdenka7316b02005-05-12 22:48:09 +0000329
330/*-----------------------------------------------------------------------
331 * SIUMCR - SIU Module Configuration 4-31
332 *-----------------------------------------------------------------------
333 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200334#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
wdenka7316b02005-05-12 22:48:09 +0000335
336/*-----------------------------------------------------------------------
337 * SYPCR - System Protection Control 4-35
338 * SYPCR can only be written once after reset!
339 *-----------------------------------------------------------------------
340 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
341 */
342#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200343#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenka7316b02005-05-12 22:48:09 +0000344 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
345#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200346#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenka7316b02005-05-12 22:48:09 +0000347 SYPCR_SWRI|SYPCR_SWP)
348#endif /* CONFIG_WATCHDOG */
349
350/*-----------------------------------------------------------------------
351 * TMCNTSC - Time Counter Status and Control 4-40
352 *-----------------------------------------------------------------------
353 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
354 * and enable Time Counter
355 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200356#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenka7316b02005-05-12 22:48:09 +0000357
358/*-----------------------------------------------------------------------
359 * PISCR - Periodic Interrupt Status and Control 4-42
360 *-----------------------------------------------------------------------
361 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
362 * Periodic timer
363 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200364#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenka7316b02005-05-12 22:48:09 +0000365
366/*-----------------------------------------------------------------------
367 * SCCR - System Clock Control 9-8
368 *-----------------------------------------------------------------------
369 * Ensure DFBRG is Divide by 16
370 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200371#define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01)
wdenka7316b02005-05-12 22:48:09 +0000372
373/*-----------------------------------------------------------------------
374 * RCCR - RISC Controller Configuration 13-7
375 *-----------------------------------------------------------------------
376 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200377#define CONFIG_SYS_RCCR 0
wdenka7316b02005-05-12 22:48:09 +0000378
379/*
380 * Init Memory Controller:
381 *
382 * Bank Bus Machine PortSz Device
383 * ---- --- ------- ------ ------
384 * 0 60x GPCM 16 bit FLASH
385 * 1 60x GPCM 8 bit NAND
386 * 2 60x SDRAM 32 bit SDRAM
387 * 3 60x GPCM 8 bit UART
388 *
389 */
390
391#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
392
393/* Minimum mask to separate preliminary
394 * address ranges for CS[0:2]
395 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200396#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */
wdenka7316b02005-05-12 22:48:09 +0000397
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200398#define CONFIG_SYS_MPTPR 0x6600
wdenka7316b02005-05-12 22:48:09 +0000399
400/*-----------------------------------------------------------------------------
401 * Address for Mode Register Set (MRS) command
402 *-----------------------------------------------------------------------------
403 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200404#define CONFIG_SYS_MRS_OFFS 0x00000110
wdenka7316b02005-05-12 22:48:09 +0000405
406
407/* Bank 0 - FLASH
408 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200409#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
wdenka7316b02005-05-12 22:48:09 +0000410 BRx_PS_8 |\
411 BRx_MS_GPCM_P |\
412 BRx_V)
413
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200414#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
wdenka7316b02005-05-12 22:48:09 +0000415 ORxG_SCY_6_CLK )
416
Jon Loeligerb1840de2007-07-08 13:46:18 -0500417#if defined(CONFIG_CMD_NAND)
wdenka7316b02005-05-12 22:48:09 +0000418/* Bank 1 - NAND Flash
419*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200420#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE
421#define CONFIG_SYS_NAND_SIZE 0x8000
wdenka7316b02005-05-12 22:48:09 +0000422
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200423#define CONFIG_SYS_OR_TIMING_NAND 0x000036
wdenka7316b02005-05-12 22:48:09 +0000424
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200425#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
426#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
wdenka7316b02005-05-12 22:48:09 +0000427#endif
428
429/* Bank 2 - 60x bus SDRAM
430 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200431#define CONFIG_SYS_PSRT 0x20
432#define CONFIG_SYS_LSRT 0x20
wdenka7316b02005-05-12 22:48:09 +0000433
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200434#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenka7316b02005-05-12 22:48:09 +0000435 BRx_PS_32 |\
436 BRx_MS_SDRAM_P |\
437 BRx_V)
438
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200439#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2
wdenka7316b02005-05-12 22:48:09 +0000440
441
442/* SDRAM initialization values
443*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200444#define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
wdenka7316b02005-05-12 22:48:09 +0000445 ORxS_BPD_4 |\
Sergej Stepanovfff10d42007-10-17 11:18:42 +0200446 ORxS_ROWST_PBI0_A9 |\
wdenka7316b02005-05-12 22:48:09 +0000447 ORxS_NUMR_12)
448
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200449#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
wdenka7316b02005-05-12 22:48:09 +0000450 PSDMR_BSMA_A15_A17 |\
Sergej Stepanovfff10d42007-10-17 11:18:42 +0200451 PSDMR_SDA10_PBI0_A10 |\
wdenka7316b02005-05-12 22:48:09 +0000452 PSDMR_RFRC_5_CLK |\
453 PSDMR_PRETOACT_2W |\
454 PSDMR_ACTTORW_2W |\
455 PSDMR_BL |\
456 PSDMR_LDOTOPRE_2C |\
457 PSDMR_WRC_3C |\
458 PSDMR_CL_3)
459
460/* Bank 3 - UART
461*/
462
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200463#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
464#define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
wdenka7316b02005-05-12 22:48:09 +0000465
466#endif /* __CONFIG_H */