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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Simon Glass9d5d1cc2015-08-30 16:55:42 -06002/*
3 * Google Veyron (and derivatives) board device tree source
4 *
5 * Copyright 2014 Google, Inc
Simon Glass9d5d1cc2015-08-30 16:55:42 -06006 */
7
8#include <dt-bindings/clock/rockchip,rk808.h>
9#include <dt-bindings/input/input.h>
10#include "rk3288.dtsi"
11
12/ {
13 memory {
14 reg = <0x0 0x80000000>;
15 };
16
17 chosen {
18 stdout-path = &uart2;
Simon Glass9d5d1cc2015-08-30 16:55:42 -060019 };
20
21 firmware {
22 chromeos {
23 pinctrl-names = "default";
24 pinctrl-0 = <&fw_wp_ap>;
25 write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
26 };
27 };
28
29 backlight: backlight {
30 compatible = "pwm-backlight";
31 brightness-levels = <
32 0 1 2 3 4 5 6 7
33 8 9 10 11 12 13 14 15
34 16 17 18 19 20 21 22 23
35 24 25 26 27 28 29 30 31
36 32 33 34 35 36 37 38 39
37 40 41 42 43 44 45 46 47
38 48 49 50 51 52 53 54 55
39 56 57 58 59 60 61 62 63
40 64 65 66 67 68 69 70 71
41 72 73 74 75 76 77 78 79
42 80 81 82 83 84 85 86 87
43 88 89 90 91 92 93 94 95
44 96 97 98 99 100 101 102 103
45 104 105 106 107 108 109 110 111
46 112 113 114 115 116 117 118 119
47 120 121 122 123 124 125 126 127
48 128 129 130 131 132 133 134 135
49 136 137 138 139 140 141 142 143
50 144 145 146 147 148 149 150 151
51 152 153 154 155 156 157 158 159
52 160 161 162 163 164 165 166 167
53 168 169 170 171 172 173 174 175
54 176 177 178 179 180 181 182 183
55 184 185 186 187 188 189 190 191
56 192 193 194 195 196 197 198 199
57 200 201 202 203 204 205 206 207
58 208 209 210 211 212 213 214 215
59 216 217 218 219 220 221 222 223
60 224 225 226 227 228 229 230 231
61 232 233 234 235 236 237 238 239
62 240 241 242 243 244 245 246 247
63 248 249 250 251 252 253 254 255>;
64 default-brightness-level = <128>;
65 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
66 backlight-boot-off;
67 pinctrl-names = "default";
68 pinctrl-0 = <&bl_en>;
69 pwms = <&pwm0 0 1000000 0>;
70 };
71
72 panel: panel {
73 compatible ="cnm,n116bgeea2","simple-panel";
74 status = "okay";
75 power-supply = <&vcc33_lcd>;
76 backlight = <&backlight>;
77 };
78
79 gpio_keys: gpio-keys {
80 compatible = "gpio-keys";
Simon Glass9d5d1cc2015-08-30 16:55:42 -060081
82 pinctrl-names = "default";
83 pinctrl-0 = <&pwr_key_h>;
84 power {
85 label = "Power";
86 gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
87 linux,code = <KEY_POWER>;
88 debounce-interval = <100>;
89 gpio-key,wakeup;
90 };
91 };
92
93 gpio-restart {
94 compatible = "gpio-restart";
95 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&ap_warm_reset_h>;
98 priority = /bits/ 8 <200>;
99 };
100
Simon Glassaf0b7442016-01-21 19:43:36 -0700101 emmc_pwrseq: emmc-pwrseq {
102 compatible = "mmc-pwrseq-emmc";
103 pinctrl-0 = <&emmc_reset>;
104 pinctrl-names = "default";
105 reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
106 };
107
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600108 sound {
109 compatible = "rockchip,rockchip-audio-max98090";
110 rockchip,model = "ROCKCHIP-I2S";
111 rockchip,i2s-controller = <&i2s>;
112 rockchip,audio-codec = <&max98090>;
113 rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
114 rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
115 rockchip,headset-codec = <&headsetcodec>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&mic_det>, <&hp_det>;
118 };
119
120 vdd_logic: pwm-regulator {
121 compatible = "pwm-regulator";
122 pwms = <&pwm1 0 2000 0>;
123
124 voltage-table = <1350000 0>,
125 <1300000 10>,
126 <1250000 20>,
127 <1200000 31>,
128 <1150000 41>,
129 <1100000 52>,
130 <1050000 62>,
131 <1000000 72>,
132 < 950000 83>;
133
134 regulator-min-microvolt = <950000>;
135 regulator-max-microvolt = <1350000>;
136 regulator-name = "vdd_logic";
137 regulator-ramp-delay = <4000>;
138 };
139
140 vcc33_sys: vcc33-sys {
141 compatible = "regulator-fixed";
142 regulator-name = "vcc33_sys";
143 regulator-always-on;
144 regulator-boot-on;
145 regulator-min-microvolt = <3300000>;
146 regulator-max-microvolt = <3300000>;
147 vin-supply = <&vccsys>;
148 };
149
150 vcc_5v: vcc-5v {
151 compatible = "regulator-fixed";
152 regulator-name = "vcc_5v";
153 regulator-always-on;
154 regulator-boot-on;
155 regulator-min-microvolt = <5000000>;
156 regulator-max-microvolt = <5000000>;
157 };
158
159 vcc50_hdmi: vcc50-hdmi {
160 compatible = "regulator-fixed";
161 regulator-name = "vcc50_hdmi";
162 regulator-always-on;
163 regulator-boot-on;
164 vin-supply = <&vcc_5v>;
165 };
166
167 bt_regulator: bt-regulator {
168 /*
169 * On the module itself this is one of these (depending
170 * on the actual card pouplated):
171 * - BT_I2S_WS_BT_RFDISABLE_L
172 * - No connect
173 */
174
175 compatible = "regulator-fixed";
176 enable-active-high;
177 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&bt_enable_l>;
180 regulator-name = "bt_regulator";
181 };
182
183 wifi_regulator: wifi-regulator {
184 /*
185 * On the module itself this is one of these (depending
186 * on the actual card populated):
187 * - SDIO_RESET_L_WL_REG_ON
188 * - PDN (power down when low)
189 */
190
191 compatible = "regulator-fixed";
192 enable-active-high;
193 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&wifi_enable_h>;
196 regulator-name = "wifi_regulator";
197
198 /* Faux input supply. See bt_regulator description. */
199 vin-supply = <&bt_regulator>;
200 };
201
202 io-domains {
203 compatible = "rockchip,rk3288-io-voltage-domain";
204 rockchip,grf = <&grf>;
205
206 audio-supply = <&vcc18_codec>;
207 bb-supply = <&vcc33_io>;
208 dvp-supply = <&vcc_18>;
209 flash0-supply = <&vcc18_flashio>;
210 gpio1830-supply = <&vcc33_io>;
211 gpio30-supply = <&vcc33_io>;
212 lcdc-supply = <&vcc33_lcd>;
213 sdcard-supply = <&vccio_sd>;
214 wifi-supply = <&vcc18_wl>;
215 };
216};
217
218&cpu0 {
219 cpu0-supply = <&vdd_cpu>;
220};
221
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600222&efuse {
223 status = "okay";
224};
225
226&emmc {
227 broken-cd;
228 bus-width = <8>;
229 cap-mmc-highspeed;
230 mmc-hs200-1_8v;
Simon Glassaf0b7442016-01-21 19:43:36 -0700231 mmc-pwrseq = <&emmc_pwrseq>;
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600232 disable-wp;
233 non-removable;
234 num-slots = <1>;
235 pinctrl-names = "default";
Simon Glassaf0b7442016-01-21 19:43:36 -0700236 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>;
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600237 status = "okay";
238};
239
240&sdio0 {
241 broken-cd;
242 bus-width = <4>;
243 cap-sd-highspeed;
244 sd-uhs-sdr12;
245 sd-uhs-sdr25;
246 sd-uhs-sdr50;
247 sd-uhs-sdr104;
248 cap-sdio-irq;
249 card-external-vcc-supply = <&wifi_regulator>;
250 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>,
251 <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>;
252 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock";
253 keep-power-in-suspend;
254 non-removable;
255 num-slots = <1>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
258 status = "okay";
259 vmmc-supply = <&vcc33_sys>;
260 vqmmc-supply = <&vcc18_wl>;
261};
262
263&sdmmc {
264 bus-width = <4>;
265 cap-mmc-highspeed;
266 cap-sd-highspeed;
267 sd-uhs-sdr12;
268 sd-uhs-sdr25;
269 sd-uhs-sdr50;
270 sd-uhs-sdr104;
271 card-detect-delay = <200>;
272 cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
273 num-slots = <1>;
274 status = "okay";
275 vmmc-supply = <&vcc33_sd>;
276 vqmmc-supply = <&vccio_sd>;
277};
278
279&spi2 {
280 status = "okay";
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600281
282 spi_flash: spiflash@0 {
Neil Armstronga009fa72019-02-10 10:16:20 +0000283 compatible = "spidev", "jedec,spi-nor";
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600284 spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
285 reg = <0>;
286 };
287};
288
289&i2c0 {
290 status = "okay";
291
292 clock-frequency = <400000>;
293 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
294 i2c-scl-rising-time-ns = <100>; /* 45ns measured */
295
296 rk808: pmic@1b {
297 compatible = "rockchip,rk808";
298 clock-output-names = "xin32k", "wifibt_32kin";
299 interrupt-parent = <&gpio0>;
300 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pmic_int_l>;
303 reg = <0x1b>;
304 rockchip,system-power-controller;
305 wakeup-source;
306 #clock-cells = <1>;
307
308 vcc1-supply = <&vcc33_sys>;
309 vcc2-supply = <&vcc33_sys>;
310 vcc3-supply = <&vcc33_sys>;
311 vcc4-supply = <&vcc33_sys>;
312 vcc6-supply = <&vcc_5v>;
313 vcc7-supply = <&vcc33_sys>;
314 vcc8-supply = <&vcc33_sys>;
315 vcc9-supply = <&vcc_5v>;
316 vcc10-supply = <&vcc33_sys>;
317 vcc11-supply = <&vcc_5v>;
318 vcc12-supply = <&vcc_18>;
319
320 vddio-supply = <&vcc33_io>;
321
322 regulators {
323 vdd_cpu: DCDC_REG1 {
324 regulator-always-on;
325 regulator-boot-on;
326 regulator-min-microvolt = <750000>;
327 regulator-max-microvolt = <1450000>;
328 regulator-name = "vdd_arm";
329 regulator-ramp-delay = <6001>;
330 regulator-suspend-mem-disabled;
331 };
332
333 vdd_gpu: DCDC_REG2 {
334 regulator-always-on;
335 regulator-boot-on;
336 regulator-min-microvolt = <800000>;
337 regulator-max-microvolt = <1250000>;
338 regulator-name = "vdd_gpu";
339 regulator-ramp-delay = <6001>;
340 regulator-suspend-mem-disabled;
341 };
342
343 vcc135_ddr: DCDC_REG3 {
344 regulator-always-on;
345 regulator-boot-on;
346 regulator-name = "vcc135_ddr";
347 regulator-suspend-mem-enabled;
348 };
349
350 /*
351 * vcc_18 has several aliases. (vcc18_flashio and
352 * vcc18_wl). We'll add those aliases here just to
353 * make it easier to follow the schematic. The signals
354 * are actually hooked together and only separated for
355 * power measurement purposes).
356 */
357 vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
358 regulator-always-on;
359 regulator-boot-on;
360 regulator-min-microvolt = <1800000>;
361 regulator-max-microvolt = <1800000>;
362 regulator-name = "vcc_18";
363 regulator-suspend-mem-microvolt = <1800000>;
364 };
365
366 /*
367 * Note that both vcc33_io and vcc33_pmuio are always
368 * powered together. To simplify the logic in the dts
369 * we just refer to vcc33_io every time something is
370 * powered from vcc33_pmuio. In fact, on later boards
371 * (such as danger) they're the same net.
372 */
373 vcc33_io: LDO_REG1 {
374 regulator-always-on;
375 regulator-boot-on;
376 regulator-min-microvolt = <3300000>;
377 regulator-max-microvolt = <3300000>;
378 regulator-name = "vcc33_io";
379 regulator-suspend-mem-microvolt = <3300000>;
380 };
381
382 vdd_10: LDO_REG3 {
383 regulator-always-on;
384 regulator-boot-on;
385 regulator-min-microvolt = <1000000>;
386 regulator-max-microvolt = <1000000>;
387 regulator-name = "vdd_10";
388 regulator-suspend-mem-microvolt = <1000000>;
389 };
390
391 vccio_sd: LDO_REG4 {
392 regulator-min-microvolt = <1800000>;
393 regulator-max-microvolt = <3300000>;
394 regulator-name = "vccio_sd";
395 regulator-suspend-mem-disabled;
396 };
397
398 vcc33_sd: LDO_REG5 {
399 regulator-min-microvolt = <3300000>;
400 regulator-max-microvolt = <3300000>;
401 regulator-name = "vcc33_sd";
402 regulator-suspend-mem-disabled;
403 };
404
405 vcc18_codec: LDO_REG6 {
406 regulator-always-on;
407 regulator-boot-on;
408 regulator-min-microvolt = <1800000>;
409 regulator-max-microvolt = <1800000>;
410 regulator-name = "vcc18_codec";
411 regulator-suspend-mem-disabled;
412 };
413
414 vdd10_lcd_pwren_h: LDO_REG7 {
415 regulator-always-on;
416 regulator-boot-on;
417 regulator-min-microvolt = <2500000>;
418 regulator-max-microvolt = <2500000>;
419 regulator-name = "vdd10_lcd_pwren_h";
420 regulator-suspend-mem-disabled;
421 };
422
423 vcc33_lcd: SWITCH_REG1 {
424 regulator-always-on;
425 regulator-boot-on;
426 regulator-name = "vcc33_lcd";
427 regulator-suspend-mem-disabled;
428 };
429 };
430 };
431};
432
433&i2c1 {
434 status = "okay";
435
436 clock-frequency = <400000>;
437 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
438 i2c-scl-rising-time-ns = <100>; /* 40ns measured */
439
440 tpm: tpm@20 {
441 compatible = "infineon,slb9645tt";
442 reg = <0x20>;
443 powered-while-suspended;
444 };
445};
446
447&i2c2 {
448 status = "okay";
449
450 /* 100kHz since 4.7k resistors don't rise fast enough */
451 clock-frequency = <100000>;
452 i2c-scl-falling-time-ns = <50>; /* 10ns measured */
453 i2c-scl-rising-time-ns = <800>; /* 600ns measured */
454
455 max98090: max98090@10 {
456 compatible = "maxim,max98090";
457 reg = <0x10>;
Simon Glassb7e0e852018-12-27 20:15:23 -0700458 #sound-dai-cells = <0>;
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600459 interrupt-parent = <&gpio6>;
460 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&int_codec>;
463 };
464};
465
466&i2c3 {
467 status = "okay";
468
469 clock-frequency = <400000>;
470 i2c-scl-falling-time-ns = <50>;
471 i2c-scl-rising-time-ns = <300>;
472};
473
474&i2c4 {
475 status = "okay";
476
477 clock-frequency = <400000>;
478 i2c-scl-falling-time-ns = <50>; /* 11ns measured */
479 i2c-scl-rising-time-ns = <300>; /* 225ns measured */
480
481 headsetcodec: ts3a227e@3b {
482 compatible = "ti,ts3a227e";
483 reg = <0x3b>;
484 interrupt-parent = <&gpio0>;
485 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&ts3a227e_int_l>;
488 ti,micbias = <7>; /* MICBIAS = 2.8V */
489 };
490};
491
492&i2c5 {
493 status = "okay";
494
495 clock-frequency = <100000>;
496 i2c-scl-falling-time-ns = <300>;
497 i2c-scl-rising-time-ns = <1000>;
498};
499
500&i2s {
501 status = "okay";
502 clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
503 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
504};
505
506&wdt {
507 status = "okay";
508};
509
510&pwm0 {
511 status = "okay";
512};
513
514&pwm1 {
515 status = "okay";
516};
517
518&uart0 {
519 status = "okay";
520
521 /* Pins don't include flow control by default; add that in */
522 pinctrl-names = "default";
523 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
524 /* We need to go faster than 24MHz, so adjust clock parents / rates */
525 assigned-clocks = <&cru SCLK_UART0>;
526 assigned-clock-rates = <48000000>;
527};
528
529&uart1 {
530 status = "okay";
531};
532
533&uart2 {
534 status = "okay";
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600535 reg-shift = <2>;
536};
537
538&vopb {
539 status = "okay";
540};
541
542&vopb_mmu {
543 status = "okay";
544};
545
546&vopl {
547 status = "okay";
548};
549
550&vopl_mmu {
551 status = "okay";
552};
553
554&edp {
555 status = "okay";
556 rockchip,panel = <&panel>;
557};
558
559&hdmi {
560 status = "okay";
561};
562
563&hdmi_audio {
564 status = "okay";
565};
566
567&gpu {
568 status = "okay";
569};
570
571&tsadc {
572 tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
573 tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
574 status = "okay";
575};
576
577&pinctrl {
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600578 pinctrl-names = "default", "sleep";
579 pinctrl-0 = <
580 /* Common for sleep and wake, but no owners */
581 &ddr0_retention
582 &ddrio_pwroff
583 &global_pwroff
584
585 /* Wake only */
586 &bt_dev_wake_awake
587 >;
588 pinctrl-1 = <
589 /* Common for sleep and wake, but no owners */
590 &ddr0_retention
591 &ddrio_pwroff
592 &global_pwroff
593
594 /* Sleep only */
595 &bt_dev_wake_sleep
596 >;
597
598 /* Add this for sdmmc pins to SD card */
599 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
600 drive-strength = <8>;
601 };
602
603 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
604 bias-pull-up;
605 drive-strength = <8>;
606 };
607
608 pcfg_output_high: pcfg-output-high {
609 output-high;
610 };
611
612 pcfg_output_low: pcfg-output-low {
613 output-low;
614 };
615
616 backlight {
617 bl_en: bl-en {
618 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
619 };
620 };
621
622 buttons {
623 pwr_key_h: pwr-key-h {
624 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
625 };
626 };
627
628 codec {
629 hp_det: hp-det {
630 rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>;
631 };
632 int_codec: int-codec {
633 rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>;
634 };
635 mic_det: mic-det {
636 rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>;
637 };
638 };
639
640 emmc {
Simon Glassaf0b7442016-01-21 19:43:36 -0700641 emmc_reset: emmc-reset {
642 rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600643 };
644
645 /*
646 * We run eMMC at max speed; bump up drive strength.
647 * We also have external pulls, so disable the internal ones.
648 */
649 emmc_clk: emmc-clk {
650 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
651 };
652
653 emmc_cmd: emmc-cmd {
654 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
655 };
656
657 emmc_bus8: emmc-bus8 {
658 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
659 <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
660 <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
661 <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
662 <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
663 <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
664 <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
665 <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
666 };
667 };
668
669 headset {
670 ts3a227e_int_l: ts3a227e-int-l {
671 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
672 };
673 };
674
675 pmic {
676 pmic_int_l: pmic-int-l {
Simon Glass930ec982016-01-21 19:43:37 -0700677 /*
678 * Causes jerry to hang when probing bus 0
679 * rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
680 */
Simon Glass9d5d1cc2015-08-30 16:55:42 -0600681 };
682 };
683
684 reboot {
685 ap_warm_reset_h: ap-warm-reset-h {
686 rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
687 };
688 };
689
690 sdio0 {
691 wifi_enable_h: wifienable-h {
692 rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
693 };
694
695 /* NOTE: mislabelled on schematic; should be bt_enable_h */
696 bt_enable_l: bt-enable-l {
697 rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
698 };
699
700 /*
701 * We run sdio0 at max speed; bump up drive strength.
702 * We also have external pulls, so disable the internal ones.
703 */
704 sdio0_bus4: sdio0-bus4 {
705 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
706 <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
707 <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
708 <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
709 };
710
711 sdio0_cmd: sdio0-cmd {
712 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
713 };
714
715 sdio0_clk: sdio0-clk {
716 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
717 };
718
719 /*
720 * These pins are only present on very new veyron boards; on
721 * older boards bt_dev_wake is simply always high. Note that
722 * gpio4_26 is a NC on old veyron boards, so it doesn't hurt
723 * to map this pin everywhere
724 */
725 bt_dev_wake_sleep: bt-dev-wake-sleep {
726 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>;
727 };
728
729 bt_dev_wake_awake: bt-dev-wake-awake {
730 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>;
731 };
732 };
733
734 sdmmc {
735 /*
736 * We run sdmmc at max speed; bump up drive strength.
737 * We also have external pulls, so disable the internal ones.
738 */
739 sdmmc_bus4: sdmmc-bus4 {
740 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
741 <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
742 <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
743 <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
744 };
745
746 sdmmc_clk: sdmmc-clk {
747 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
748 };
749
750 sdmmc_cmd: sdmmc-cmd {
751 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
752 };
753
754 /*
755 * Builtin CD line is hooked to ground to prevent JTAG at boot
756 * (and also to get the voltage rail correct). Make we
757 * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
758 * think there's a card inserted
759 */
760 sdmmc_cd_disabled: sdmmc-cd-disabled {
761 rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>;
762 };
763
764 /* This is where we actually hook up CD */
765 sdmmc_cd_gpio: sdmmc-cd-gpio {
766 rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>;
767 };
768 };
769
770 tpm {
771 tpm_int_h: tpm-int-h {
772 rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
773 };
774 };
775
776 write-protect {
777 fw_wp_ap: fw-wp-ap {
778 rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
779 };
780 };
781};
782
783&usbphy {
784 status = "okay";
785};
786
787&usb_host0_ehci {
788 status = "okay";
789 needs-reset-on-resume;
790};
791
792&usb_host1 {
793 status = "okay";
794};
795
796&usb_otg {
797 dr_mode = "host";
798 status = "okay";
799 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
800 assigned-clock-parents = <&cru SCLK_OTGPHY0>;
801};