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git01.mediatek.com / filogic / uboot / b83019fad9c57c7310fb05d787f1afd254b77e3f / . / board / xilinx / zynqmp / tap_delays.c
blob: d16bbb8eff9e340f7670f06d71b2d5f8db848557 [file] [log] [blame]
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Xilinx ZynqMP SoC Tap Delay Programming
4 *
5 * Copyright (C) 2018 Xilinx, Inc.
6 */
7
8#include <common.h>
Ashok Reddy Soma5fe3f412020-10-23 04:59:04 -0600[diff] [blame]9#include <zynqmp_tap_delay.h>
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]10#include <asm/arch/sys_proto.h>
Simon Glassdbd79542020-05-10 11:40:11 -0600[diff] [blame]11#include <linux/delay.h>
Ashok Reddy Soma0afdfe32020-10-23 04:58:58 -0600[diff] [blame]12#include <mmc.h>
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]13
14#define SD_DLL_CTRL 0xFF180358
15#define SD_ITAP_DLY 0xFF180314
16#define SD_OTAP_DLY 0xFF180318
17#define SD0_DLL_RST_MASK 0x00000004
18#define SD0_DLL_RST 0x00000004
19#define SD1_DLL_RST_MASK 0x00040000
20#define SD1_DLL_RST 0x00040000
21#define SD0_ITAPCHGWIN_MASK 0x00000200
22#define SD0_ITAPCHGWIN 0x00000200
23#define SD1_ITAPCHGWIN_MASK 0x02000000
24#define SD1_ITAPCHGWIN 0x02000000
25#define SD0_ITAPDLYENA_MASK 0x00000100
26#define SD0_ITAPDLYENA 0x00000100
27#define SD1_ITAPDLYENA_MASK 0x01000000
28#define SD1_ITAPDLYENA 0x01000000
29#define SD0_ITAPDLYSEL_MASK 0x000000FF
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]30#define SD1_ITAPDLYSEL_MASK 0x00FF0000
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]31#define SD0_OTAPDLYSEL_MASK 0x0000003F
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]32#define SD1_OTAPDLYSEL_MASK 0x003F0000
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]33
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]34void zynqmp_dll_reset(u8 deviceid)
35{
36 /* Issue DLL Reset */
37 if (deviceid == 0)
38 zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
39 SD0_DLL_RST);
40 else
41 zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
42 SD1_DLL_RST);
43
44 mdelay(1);
45
46 /* Release DLL Reset */
47 if (deviceid == 0)
48 zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
49 else
50 zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
51}
52
Ashok Reddy Soma39a177a2021-07-09 05:53:42 -0600[diff] [blame]53void arasan_zynqmp_set_in_tapdelay(u8 deviceid, u32 itap_delay)
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]54{
55 if (deviceid == 0) {
Ashok Reddy Soma39a177a2021-07-09 05:53:42 -0600[diff] [blame]56 zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, SD0_DLL_RST);
Ashok Reddy Soma5fe3f412020-10-23 04:59:04 -0600[diff] [blame]57
Ashok Reddy Soma39a177a2021-07-09 05:53:42 -0600[diff] [blame]58 /* Program ITAP delay */
59 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
60 SD0_ITAPCHGWIN);
61 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
62 SD0_ITAPDLYENA);
63 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK, itap_delay);
64 zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]65
Ashok Reddy Soma5fe3f412020-10-23 04:59:04 -0600[diff] [blame]66 zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]67 } else {
Ashok Reddy Soma39a177a2021-07-09 05:53:42 -0600[diff] [blame]68 zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, SD1_DLL_RST);
69
70 /* Program ITAP delay */
71 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
72 SD1_ITAPCHGWIN);
73 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
74 SD1_ITAPDLYENA);
75 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
76 (itap_delay << 16));
77 zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
78
79 zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
80 }
81}
82
83void arasan_zynqmp_set_out_tapdelay(u8 deviceid, u32 otap_delay)
84{
85 if (deviceid == 0) {
86 zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, SD0_DLL_RST);
87
88 /* Program OTAP delay */
89 zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK, otap_delay);
90
91 zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
92 } else {
93 zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, SD1_DLL_RST);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]94
Ashok Reddy Soma39a177a2021-07-09 05:53:42 -0600[diff] [blame]95 /* Program OTAP delay */
96 zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
97 (otap_delay << 16));
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]98
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]99 zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
Ashok Reddy Soma5fe3f412020-10-23 04:59:04 -0600[diff] [blame]100 }
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]101}