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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Shengzhou Liuf13321d2014-03-05 15:04:48 +08002/*
3 * Copyright 2014 Freescale Semiconductor
Shengzhou Liuf13321d2014-03-05 15:04:48 +08004 */
5
6/*
7 * CPLD register set of T2080RDB board-specific.
8 */
9struct cpld_data {
10 u8 chip_id1; /* 0x00 - Chip ID1 register */
11 u8 chip_id2; /* 0x01 - Chip ID2 register */
12 u8 hw_ver; /* 0x02 - Hardware Revision Register */
13 u8 sw_ver; /* 0x03 - Software Revision register */
14 u8 res0[12]; /* 0x04 - 0x0F - not used */
15 u8 reset_ctl; /* 0x10 - Reset control Register */
16 u8 flash_csr; /* 0x11 - Flash control and status register */
17 u8 thermal_csr; /* 0x12 - Thermal control and status register */
18 u8 led_csr; /* 0x13 - LED control and status register */
19 u8 sfp_csr; /* 0x14 - SFP+ control and status register */
20 u8 misc_csr; /* 0x15 - Misc control and status register */
21 u8 boot_or; /* 0x16 - Boot config override register */
22 u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */
23 u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */
Tom Rinid3ba2a22021-05-03 16:48:54 -040024};
Shengzhou Liuf13321d2014-03-05 15:04:48 +080025
26u8 cpld_read(unsigned int reg);
27void cpld_write(unsigned int reg, u8 value);
28
29#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
30#define CPLD_WRITE(reg, value) \
31 cpld_write(offsetof(struct cpld_data, reg), value)
32
33/* CPLD on IFC */
34#define CPLD_LBMAP_MASK 0x3F
35#define CPLD_BANK_SEL_MASK 0x07
36#define CPLD_BANK_OVERRIDE 0x40
Shengzhou Liu14139832014-04-18 16:43:41 +080037#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
38#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
Shengzhou Liuf13321d2014-03-05 15:04:48 +080039#define CPLD_LBMAP_RESET 0xFF
40#define CPLD_LBMAP_SHIFT 0x03
41#define CPLD_BOOT_SEL 0x80
Shengzhou Liud703f662015-04-22 10:59:50 +080042
43/* RSTCON Register */
44#define CPLD_RSTCON_EDC_RST 0x04