blob: 76bbb6087afdc354b56a8b69a79c5b5fa7f01a09 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Shaohui Xiedd335672015-11-11 17:58:37 +08002/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
Biwen Lib41f6ba2020-07-02 11:13:03 +08004 * Copyright 2019-2020 NXP
Shaohui Xiedd335672015-11-11 17:58:37 +08005 */
6
7#include <common.h>
8#include <i2c.h>
9#include <fdt_support.h>
Simon Glass0e0ac202017-04-06 12:47:04 -060010#include <fsl_ddr_sdram.h>
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
Shaohui Xiedd335672015-11-11 17:58:37 +080014#include <asm/io.h>
15#include <asm/arch/clock.h>
16#include <asm/arch/fsl_serdes.h>
Hou Zhiqiang09fd9452017-04-14 14:48:21 +080017#include <asm/arch/ppa.h>
Shaohui Xiedd335672015-11-11 17:58:37 +080018#include <asm/arch/fdt.h>
York Sun729f2d12017-03-06 09:02:34 -080019#include <asm/arch/mmu.h>
Rajesh Bhagat90bde112018-11-05 18:02:48 +000020#include <asm/arch/cpu.h>
Shaohui Xiedd335672015-11-11 17:58:37 +080021#include <asm/arch/soc.h>
Laurentiu Tudor22012d52018-08-27 17:33:59 +030022#include <asm/arch-fsl-layerscape/fsl_icid.h>
Shaohui Xiedd335672015-11-11 17:58:37 +080023#include <ahci.h>
24#include <hwconfig.h>
25#include <mmc.h>
26#include <scsi.h>
27#include <fm_eth.h>
Shaohui Xiedd335672015-11-11 17:58:37 +080028#include <fsl_esdhc.h>
29#include <fsl_ifc.h>
30#include <spl.h>
Stephen Carlson7ee444a2021-06-22 16:39:31 -070031#include "../common/i2c_mux.h"
Shaohui Xiedd335672015-11-11 17:58:37 +080032
33#include "../common/qixis.h"
34#include "ls1043aqds_qixis.h"
35
36DECLARE_GLOBAL_DATA_PTR;
37
38enum {
39 MUX_TYPE_GPIO,
40};
41
42/* LS1043AQDS serdes mux */
43#define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
44#define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
45#define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
46#define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
47#define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
48#define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
49#define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
50#define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
Shaohui Xiedb1ab382016-01-21 17:14:53 +080051#define CFG_UART_MUX_MASK 0x6
52#define CFG_UART_MUX_SHIFT 1
53#define CFG_LPUART_EN 0x1
Shaohui Xiedd335672015-11-11 17:58:37 +080054
Biwen Li438c37c2020-07-02 11:13:04 +080055#ifdef CONFIG_SYS_I2C_EARLY_INIT
56void i2c_early_init_f(void);
57#endif
58
Rajesh Bhagat90bde112018-11-05 18:02:48 +000059#ifdef CONFIG_TFABOOT
60struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
61 {
62 "nor0",
63 CONFIG_SYS_NOR0_CSPR,
64 CONFIG_SYS_NOR0_CSPR_EXT,
65 CONFIG_SYS_NOR_AMASK,
66 CONFIG_SYS_NOR_CSOR,
67 {
68 CONFIG_SYS_NOR_FTIM0,
69 CONFIG_SYS_NOR_FTIM1,
70 CONFIG_SYS_NOR_FTIM2,
71 CONFIG_SYS_NOR_FTIM3
72 },
73
74 },
75 {
76 "nor1",
77 CONFIG_SYS_NOR1_CSPR,
78 CONFIG_SYS_NOR1_CSPR_EXT,
79 CONFIG_SYS_NOR_AMASK,
80 CONFIG_SYS_NOR_CSOR,
81 {
82 CONFIG_SYS_NOR_FTIM0,
83 CONFIG_SYS_NOR_FTIM1,
84 CONFIG_SYS_NOR_FTIM2,
85 CONFIG_SYS_NOR_FTIM3
86 },
87 },
88 {
89 "nand",
90 CONFIG_SYS_NAND_CSPR,
91 CONFIG_SYS_NAND_CSPR_EXT,
92 CONFIG_SYS_NAND_AMASK,
93 CONFIG_SYS_NAND_CSOR,
94 {
95 CONFIG_SYS_NAND_FTIM0,
96 CONFIG_SYS_NAND_FTIM1,
97 CONFIG_SYS_NAND_FTIM2,
98 CONFIG_SYS_NAND_FTIM3
99 },
100 },
101 {
102 "fpga",
103 CONFIG_SYS_FPGA_CSPR,
104 CONFIG_SYS_FPGA_CSPR_EXT,
105 CONFIG_SYS_FPGA_AMASK,
106 CONFIG_SYS_FPGA_CSOR,
107 {
108 CONFIG_SYS_FPGA_FTIM0,
109 CONFIG_SYS_FPGA_FTIM1,
110 CONFIG_SYS_FPGA_FTIM2,
111 CONFIG_SYS_FPGA_FTIM3
112 },
113 }
114};
115
116struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
117 {
118 "nand",
119 CONFIG_SYS_NAND_CSPR,
120 CONFIG_SYS_NAND_CSPR_EXT,
121 CONFIG_SYS_NAND_AMASK,
122 CONFIG_SYS_NAND_CSOR,
123 {
124 CONFIG_SYS_NAND_FTIM0,
125 CONFIG_SYS_NAND_FTIM1,
126 CONFIG_SYS_NAND_FTIM2,
127 CONFIG_SYS_NAND_FTIM3
128 },
129 },
130 {
131 "nor0",
132 CONFIG_SYS_NOR0_CSPR,
133 CONFIG_SYS_NOR0_CSPR_EXT,
134 CONFIG_SYS_NOR_AMASK,
135 CONFIG_SYS_NOR_CSOR,
136 {
137 CONFIG_SYS_NOR_FTIM0,
138 CONFIG_SYS_NOR_FTIM1,
139 CONFIG_SYS_NOR_FTIM2,
140 CONFIG_SYS_NOR_FTIM3
141 },
142 },
143 {
144 "nor1",
145 CONFIG_SYS_NOR1_CSPR,
146 CONFIG_SYS_NOR1_CSPR_EXT,
147 CONFIG_SYS_NOR_AMASK,
148 CONFIG_SYS_NOR_CSOR,
149 {
150 CONFIG_SYS_NOR_FTIM0,
151 CONFIG_SYS_NOR_FTIM1,
152 CONFIG_SYS_NOR_FTIM2,
153 CONFIG_SYS_NOR_FTIM3
154 },
155 },
156 {
157 "fpga",
158 CONFIG_SYS_FPGA_CSPR,
159 CONFIG_SYS_FPGA_CSPR_EXT,
160 CONFIG_SYS_FPGA_AMASK,
161 CONFIG_SYS_FPGA_CSOR,
162 {
163 CONFIG_SYS_FPGA_FTIM0,
164 CONFIG_SYS_FPGA_FTIM1,
165 CONFIG_SYS_FPGA_FTIM2,
166 CONFIG_SYS_FPGA_FTIM3
167 },
168 }
169};
170
171void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
172{
173 enum boot_src src = get_boot_src();
174
175 if (src == BOOT_SOURCE_IFC_NAND)
176 regs_info->regs = ifc_cfg_nand_boot;
177 else
178 regs_info->regs = ifc_cfg_nor_boot;
179 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
180}
181#endif
182
Shaohui Xiedd335672015-11-11 17:58:37 +0800183int checkboard(void)
184{
Rajesh Bhagat90bde112018-11-05 18:02:48 +0000185#ifdef CONFIG_TFABOOT
186 enum boot_src src = get_boot_src();
187#endif
Shaohui Xiedd335672015-11-11 17:58:37 +0800188 char buf[64];
Qianyu Gong68d75202016-06-13 11:20:30 +0800189#ifndef CONFIG_SD_BOOT
Shaohui Xiedd335672015-11-11 17:58:37 +0800190 u8 sw;
191#endif
192
193 puts("Board: LS1043AQDS, boot from ");
194
Rajesh Bhagat90bde112018-11-05 18:02:48 +0000195#ifdef CONFIG_TFABOOT
196 if (src == BOOT_SOURCE_SD_MMC)
197 puts("SD\n");
198 else {
199#endif
200
Shaohui Xiedd335672015-11-11 17:58:37 +0800201#ifdef CONFIG_SD_BOOT
202 puts("SD\n");
203#else
204 sw = QIXIS_READ(brdcfg[0]);
205 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
206
207 if (sw < 0x8)
208 printf("vBank: %d\n", sw);
209 else if (sw == 0x8)
210 puts("PromJet\n");
211 else if (sw == 0x9)
212 puts("NAND\n");
Qianyu Gong68d75202016-06-13 11:20:30 +0800213 else if (sw == 0xF)
214 printf("QSPI\n");
Shaohui Xiedd335672015-11-11 17:58:37 +0800215 else
216 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
217#endif
218
Rajesh Bhagat90bde112018-11-05 18:02:48 +0000219#ifdef CONFIG_TFABOOT
220 }
221#endif
Shaohui Xiedd335672015-11-11 17:58:37 +0800222 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
223 QIXIS_READ(id), QIXIS_READ(arch));
224
225 printf("FPGA: v%d (%s), build %d\n",
226 (int)QIXIS_READ(scver), qixis_read_tag(buf),
227 (int)qixis_read_minor());
228
229 return 0;
230}
231
232bool if_board_diff_clk(void)
233{
234 u8 diff_conf = QIXIS_READ(brdcfg[11]);
235
236 return diff_conf & 0x40;
237}
238
239unsigned long get_board_sys_clk(void)
240{
241 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
242
243 switch (sysclk_conf & 0x0f) {
244 case QIXIS_SYSCLK_64:
245 return 64000000;
246 case QIXIS_SYSCLK_83:
247 return 83333333;
248 case QIXIS_SYSCLK_100:
249 return 100000000;
250 case QIXIS_SYSCLK_125:
251 return 125000000;
252 case QIXIS_SYSCLK_133:
253 return 133333333;
254 case QIXIS_SYSCLK_150:
255 return 150000000;
256 case QIXIS_SYSCLK_160:
257 return 160000000;
258 case QIXIS_SYSCLK_166:
259 return 166666666;
260 }
261
262 return 66666666;
263}
264
265unsigned long get_board_ddr_clk(void)
266{
267 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
268
269 if (if_board_diff_clk())
270 return get_board_sys_clk();
271 switch ((ddrclk_conf & 0x30) >> 4) {
272 case QIXIS_DDRCLK_100:
273 return 100000000;
274 case QIXIS_DDRCLK_125:
275 return 125000000;
276 case QIXIS_DDRCLK_133:
277 return 133333333;
278 }
279
280 return 66666666;
281}
282
Shaohui Xiedd335672015-11-11 17:58:37 +0800283int dram_init(void)
284{
285 /*
286 * When resuming from deep sleep, the I2C channel may not be
287 * in the default channel. So, switch to the default channel
288 * before accessing DDR SPD.
Biwen Li014460b2020-02-05 22:02:16 +0800289 *
290 * PCA9547 mount on I2C1 bus
Shaohui Xiedd335672015-11-11 17:58:37 +0800291 */
Biwen Li014460b2020-02-05 22:02:16 +0800292 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
Simon Glass0e0ac202017-04-06 12:47:04 -0600293 fsl_initdram();
Rajesh Bhagat90bde112018-11-05 18:02:48 +0000294#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
295 defined(CONFIG_SPL_BUILD)
York Sun729f2d12017-03-06 09:02:34 -0800296 /* This will break-before-make MMU for DDR */
297 update_early_mmu_table();
298#endif
Shaohui Xiedd335672015-11-11 17:58:37 +0800299
300 return 0;
301}
302
303int i2c_multiplexer_select_vid_channel(u8 channel)
304{
Biwen Li014460b2020-02-05 22:02:16 +0800305 return select_i2c_ch_pca9547(channel, 0);
Shaohui Xiedd335672015-11-11 17:58:37 +0800306}
307
308void board_retimer_init(void)
309{
310 u8 reg;
Biwen Li014460b2020-02-05 22:02:16 +0800311 int bus_num = 0;
Shaohui Xiedd335672015-11-11 17:58:37 +0800312
313 /* Retimer is connected to I2C1_CH7_CH5 */
Biwen Li014460b2020-02-05 22:02:16 +0800314 select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
Shaohui Xiedd335672015-11-11 17:58:37 +0800315 reg = I2C_MUX_CH5;
Igor Opaniukf7c91762021-02-09 13:52:45 +0200316#if CONFIG_IS_ENABLED(DM_I2C)
Biwen Li014460b2020-02-05 22:02:16 +0800317 struct udevice *dev;
318 int ret;
319
320 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
321 1, &dev);
322 if (ret) {
323 printf("%s: Cannot find udev for a bus %d\n", __func__,
324 bus_num);
325 return;
326 }
327 dm_i2c_write(dev, 0, &reg, 1);
328
329 /* Access to Control/Shared register */
330 ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
331 1, &dev);
332 if (ret) {
333 printf("%s: Cannot find udev for a bus %d\n", __func__,
334 bus_num);
335 return;
336 }
337
338 reg = 0x0;
339 dm_i2c_write(dev, 0xff, &reg, 1);
340
341 /* Read device revision and ID */
342 dm_i2c_read(dev, 1, &reg, 1);
343 debug("Retimer version id = 0x%x\n", reg);
344
345 /* Enable Broadcast. All writes target all channel register sets */
346 reg = 0x0c;
347 dm_i2c_write(dev, 0xff, &reg, 1);
348
349 /* Reset Channel Registers */
350 dm_i2c_read(dev, 0, &reg, 1);
351 reg |= 0x4;
352 dm_i2c_write(dev, 0, &reg, 1);
353
354 /* Enable override divider select and Enable Override Output Mux */
355 dm_i2c_read(dev, 9, &reg, 1);
356 reg |= 0x24;
357 dm_i2c_write(dev, 9, &reg, 1);
358
359 /* Select VCO Divider to full rate (000) */
360 dm_i2c_read(dev, 0x18, &reg, 1);
361 reg &= 0x8f;
362 dm_i2c_write(dev, 0x18, &reg, 1);
363
364 /* Selects active PFD MUX Input as Re-timed Data (001) */
365 dm_i2c_read(dev, 0x1e, &reg, 1);
366 reg &= 0x3f;
367 reg |= 0x20;
368 dm_i2c_write(dev, 0x1e, &reg, 1);
369
370 /* Set data rate as 10.3125 Gbps */
371 reg = 0x0;
372 dm_i2c_write(dev, 0x60, &reg, 1);
373 reg = 0xb2;
374 dm_i2c_write(dev, 0x61, &reg, 1);
375 reg = 0x90;
376 dm_i2c_write(dev, 0x62, &reg, 1);
377 reg = 0xb3;
378 dm_i2c_write(dev, 0x63, &reg, 1);
379 reg = 0xcd;
380 dm_i2c_write(dev, 0x64, &reg, 1);
381#else
Shaohui Xiedd335672015-11-11 17:58:37 +0800382 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
383
384 /* Access to Control/Shared register */
385 reg = 0x0;
386 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
387
388 /* Read device revision and ID */
389 i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
390 debug("Retimer version id = 0x%x\n", reg);
391
392 /* Enable Broadcast. All writes target all channel register sets */
393 reg = 0x0c;
394 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
395
396 /* Reset Channel Registers */
397 i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
398 reg |= 0x4;
399 i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
400
401 /* Enable override divider select and Enable Override Output Mux */
402 i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
403 reg |= 0x24;
404 i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
405
406 /* Select VCO Divider to full rate (000) */
407 i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
408 reg &= 0x8f;
409 i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
410
411 /* Selects active PFD MUX Input as Re-timed Data (001) */
412 i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
413 reg &= 0x3f;
414 reg |= 0x20;
415 i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
416
417 /* Set data rate as 10.3125 Gbps */
418 reg = 0x0;
419 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
420 reg = 0xb2;
421 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
422 reg = 0x90;
423 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
424 reg = 0xb3;
425 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
426 reg = 0xcd;
427 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
Biwen Li014460b2020-02-05 22:02:16 +0800428#endif
Wenbin Songbc7a4fd2016-03-09 13:38:24 +0800429
430 /* Return the default channel */
Biwen Li014460b2020-02-05 22:02:16 +0800431 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
Shaohui Xiedd335672015-11-11 17:58:37 +0800432}
433
434int board_early_init_f(void)
435{
Biwen Lib41f6ba2020-07-02 11:13:03 +0800436 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
Qianyu Gong8d3d5c42016-02-16 13:12:53 +0800437#ifdef CONFIG_HAS_FSL_XHCI_USB
438 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
439 u32 usb_pwrfault;
440#endif
Shaohui Xiedb1ab382016-01-21 17:14:53 +0800441#ifdef CONFIG_LPUART
442 u8 uart;
443#endif
Qianyu Gonga92f2132016-06-13 11:20:31 +0800444
Biwen Lib41f6ba2020-07-02 11:13:03 +0800445 /*
446 * Enable secure system counter for timer
447 */
448 out_le32(cntcr, 0x1);
449
Qianyu Gonga92f2132016-06-13 11:20:31 +0800450#ifdef CONFIG_SYS_I2C_EARLY_INIT
451 i2c_early_init_f();
452#endif
Shaohui Xiedd335672015-11-11 17:58:37 +0800453 fsl_lsch2_early_init_f();
Qianyu Gong8d3d5c42016-02-16 13:12:53 +0800454
455#ifdef CONFIG_HAS_FSL_XHCI_USB
456 out_be32(&scfg->rcwpmuxcr0, 0x3333);
457 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
458 usb_pwrfault =
Shaohui Xieb8c4fc92016-05-30 14:26:55 +0800459 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
460 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
Qianyu Gong8d3d5c42016-02-16 13:12:53 +0800461 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
462 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
463#endif
464
Shaohui Xiedb1ab382016-01-21 17:14:53 +0800465#ifdef CONFIG_LPUART
466 /* We use lpuart0 as system console */
467 uart = QIXIS_READ(brdcfg[14]);
468 uart &= ~CFG_UART_MUX_MASK;
469 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
470 QIXIS_WRITE(brdcfg[14], uart);
471#endif
Shaohui Xiedd335672015-11-11 17:58:37 +0800472
473 return 0;
474}
475
476#ifdef CONFIG_FSL_DEEP_SLEEP
477/* determine if it is a warm boot */
478bool is_warm_boot(void)
479{
480#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
481 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
482
483 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
484 return 1;
485
486 return 0;
487}
488#endif
489
490int config_board_mux(int ctrl_type)
491{
492 u8 reg14;
493
494 reg14 = QIXIS_READ(brdcfg[14]);
495
496 switch (ctrl_type) {
497 case MUX_TYPE_GPIO:
498 reg14 = (reg14 & (~0x30)) | 0x20;
499 break;
500 default:
501 puts("Unsupported mux interface type\n");
502 return -1;
503 }
504
505 QIXIS_WRITE(brdcfg[14], reg14);
506
507 return 0;
508}
509
510int config_serdes_mux(void)
511{
512 return 0;
513}
514
515
516#ifdef CONFIG_MISC_INIT_R
517int misc_init_r(void)
518{
519 if (hwconfig("gpio"))
520 config_board_mux(MUX_TYPE_GPIO);
521
522 return 0;
523}
524#endif
525
526int board_init(void)
527{
Hou Zhiqiang4b23ca82016-08-02 19:03:27 +0800528#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
529 erratum_a010315();
530#endif
531
Biwen Li014460b2020-02-05 22:02:16 +0800532 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
Shaohui Xiedd335672015-11-11 17:58:37 +0800533 board_retimer_init();
534
535#ifdef CONFIG_SYS_FSL_SERDES
536 config_serdes_mux();
537#endif
538
Hou Zhiqiang09fd9452017-04-14 14:48:21 +0800539#ifdef CONFIG_FSL_LS_PPA
540 ppa_init();
541#endif
542
Shaohui Xiedd335672015-11-11 17:58:37 +0800543 return 0;
544}
545
546#ifdef CONFIG_OF_BOARD_SETUP
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900547int ft_board_setup(void *blob, struct bd_info *bd)
Shaohui Xiedd335672015-11-11 17:58:37 +0800548{
Shaohui Xie16f15fa2016-01-04 11:03:44 +0800549 u64 base[CONFIG_NR_DRAM_BANKS];
550 u64 size[CONFIG_NR_DRAM_BANKS];
Qianyu Gongd2c492a2016-07-21 12:39:27 +0800551 u8 reg;
Shaohui Xie16f15fa2016-01-04 11:03:44 +0800552
553 /* fixup DT for the two DDR banks */
554 base[0] = gd->bd->bi_dram[0].start;
555 size[0] = gd->bd->bi_dram[0].size;
556 base[1] = gd->bd->bi_dram[1].start;
557 size[1] = gd->bd->bi_dram[1].size;
558
559 fdt_fixup_memory_banks(blob, base, size, 2);
Shaohui Xiedd335672015-11-11 17:58:37 +0800560 ft_cpu_setup(blob, bd);
561
562#ifdef CONFIG_SYS_DPAA_FMAN
Madalin Bucur70848512020-04-30 15:59:58 +0300563#ifndef CONFIG_DM_ETH
Shaohui Xiedd335672015-11-11 17:58:37 +0800564 fdt_fixup_fman_ethernet(blob);
Madalin Bucur70848512020-04-30 15:59:58 +0300565#endif
Shaohui Xiedd335672015-11-11 17:58:37 +0800566 fdt_fixup_board_enet(blob);
567#endif
Qianyu Gongd2c492a2016-07-21 12:39:27 +0800568
Laurentiu Tudor22012d52018-08-27 17:33:59 +0300569 fdt_fixup_icid(blob);
570
Qianyu Gongd2c492a2016-07-21 12:39:27 +0800571 reg = QIXIS_READ(brdcfg[0]);
572 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
573
574 /* Disable IFC if QSPI is enabled */
575 if (reg == 0xF)
576 do_fixup_by_compat(blob, "fsl,ifc",
577 "status", "disabled", 8 + 1, 1);
578
Shaohui Xiedd335672015-11-11 17:58:37 +0800579 return 0;
580}
581#endif
582
583u8 flash_read8(void *addr)
584{
585 return __raw_readb(addr + 1);
586}
587
588void flash_write16(u16 val, void *addr)
589{
590 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
591
592 __raw_writew(shftval, addr);
593}
594
595u16 flash_read16(void *addr)
596{
597 u16 val = __raw_readw(addr);
598
599 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
600}
Rajesh Bhagat90bde112018-11-05 18:02:48 +0000601
Tom Rini0543c432019-11-18 20:02:08 -0500602#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
Rajesh Bhagat90bde112018-11-05 18:02:48 +0000603void *env_sf_get_env_addr(void)
604{
605 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
606}
607#endif