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Bo Shen60f3dd32013-05-12 22:40:54 +00001/*
2 * Configuation settings for the SAMA5D3xEK board.
3 *
4 * Copyright (C) 2012 - 2013 Atmel
5 *
6 * based on at91sam9m10g45ek.h by:
7 * Stelian Pop <stelian@popies.net>
8 * Lead Tech Design <www.leadtechdesign.com>
9 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
Bo Shen60f3dd32013-05-12 22:40:54 +000011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Wu, Josh42587542015-03-30 14:51:19 +080016#include "at91-sama5_common.h"
Bo Shen60f3dd32013-05-12 22:40:54 +000017
Wu, Josh3c0c6602015-08-19 19:11:19 +080018#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
19
Bo Shen60f3dd32013-05-12 22:40:54 +000020/* serial console */
21#define CONFIG_ATMEL_USART
22#define CONFIG_USART_BASE ATMEL_BASE_DBGU
23#define CONFIG_USART_ID ATMEL_ID_DBGU
24
25/*
26 * This needs to be defined for the OHCI code to work but it is defined as
27 * ATMEL_ID_UHPHS in the CPU specific header files.
28 */
29#define ATMEL_ID_UHP ATMEL_ID_UHPHS
30
31/*
32 * Specify the clock enable bit in the PMC_SCER register.
33 */
34#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
35
36/* LCD */
Bo Shen60f3dd32013-05-12 22:40:54 +000037#define LCD_BPP LCD_COLOR16
38#define LCD_OUTPUT_BPP 24
39#define CONFIG_LCD_LOGO
Bo Shen60f3dd32013-05-12 22:40:54 +000040#define CONFIG_LCD_INFO
41#define CONFIG_LCD_INFO_BELOW_LOGO
42#define CONFIG_SYS_WHITE_ON_BLACK
43#define CONFIG_ATMEL_HLCD
44#define CONFIG_ATMEL_LCD_RGB565
Bo Shen60f3dd32013-05-12 22:40:54 +000045
46/* board specific (not enough SRAM) */
47#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
48
Bo Shenb15f4f62014-07-18 16:43:08 +080049/* NOR flash */
Masahiro Yamada8cea9b52017-02-11 22:43:54 +090050#ifdef CONFIG_MTD_NOR_FLASH
Bo Shenb15f4f62014-07-18 16:43:08 +080051#define CONFIG_FLASH_CFI_DRIVER
52#define CONFIG_SYS_FLASH_CFI
53#define CONFIG_SYS_FLASH_PROTECTION
54#define CONFIG_SYS_FLASH_BASE 0x10000000
55#define CONFIG_SYS_MAX_FLASH_SECT 131
56#define CONFIG_SYS_MAX_FLASH_BANKS 1
Bo Shenb15f4f62014-07-18 16:43:08 +080057#endif
Bo Shen60f3dd32013-05-12 22:40:54 +000058
Bo Shen60f3dd32013-05-12 22:40:54 +000059/* SDRAM */
60#define CONFIG_NR_DRAM_BANKS 1
61#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
62#define CONFIG_SYS_SDRAM_SIZE 0x20000000
63
Bo Shenf92b2982013-11-15 11:12:38 +080064#ifdef CONFIG_SPL_BUILD
65#define CONFIG_SYS_INIT_SP_ADDR 0x310000
66#else
Bo Shen60f3dd32013-05-12 22:40:54 +000067#define CONFIG_SYS_INIT_SP_ADDR \
68 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shenf92b2982013-11-15 11:12:38 +080069#endif
Bo Shen60f3dd32013-05-12 22:40:54 +000070
71/* SerialFlash */
Bo Shen60f3dd32013-05-12 22:40:54 +000072
73#ifdef CONFIG_CMD_SF
74#define CONFIG_ATMEL_SPI
Bo Shen60f3dd32013-05-12 22:40:54 +000075#define CONFIG_SF_DEFAULT_SPEED 30000000
76#endif
77
78/* NAND flash */
79#define CONFIG_CMD_NAND
80
81#ifdef CONFIG_CMD_NAND
Bo Shen60f3dd32013-05-12 22:40:54 +000082#define CONFIG_NAND_ATMEL
83#define CONFIG_SYS_MAX_NAND_DEVICE 1
84#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
85/* our ALE is AD21 */
86#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
87/* our CLE is AD22 */
88#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
89#define CONFIG_SYS_NAND_ONFI_DETECTION
90/* PMECC & PMERRLOC */
91#define CONFIG_ATMEL_NAND_HWECC
92#define CONFIG_ATMEL_NAND_HW_PMECC
93#define CONFIG_PMECC_CAP 4
94#define CONFIG_PMECC_SECTOR_SIZE 512
Bo Shen60f3dd32013-05-12 22:40:54 +000095#define CONFIG_CMD_NAND_TRIMFFS
96#endif
97
98/* Ethernet Hardware */
99#define CONFIG_MACB
100#define CONFIG_RMII
Bo Shen60f3dd32013-05-12 22:40:54 +0000101#define CONFIG_NET_RETRY_COUNT 20
102#define CONFIG_MACB_SEARCH_PHY
Bo Shen6f6afad2013-06-26 10:11:06 +0800103#define CONFIG_RGMII
Bo Shen6f6afad2013-06-26 10:11:06 +0800104#define CONFIG_PHYLIB
105#define CONFIG_PHY_MICREL
106#define CONFIG_PHY_MICREL_KSZ9021
Bo Shen60f3dd32013-05-12 22:40:54 +0000107
108/* MMC */
Bo Shen60f3dd32013-05-12 22:40:54 +0000109
110#ifdef CONFIG_CMD_MMC
Bo Shen60f3dd32013-05-12 22:40:54 +0000111#define CONFIG_GENERIC_ATMEL_MCI
112#define ATMEL_BASE_MMCI ATMEL_BASE_MCI0
113#endif
114
115/* USB */
Bo Shen60f3dd32013-05-12 22:40:54 +0000116
117#ifdef CONFIG_CMD_USB
118#define CONFIG_USB_ATMEL
Bo Shen4a985df2013-10-21 16:14:00 +0800119#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Bo Shen60f3dd32013-05-12 22:40:54 +0000120#define CONFIG_USB_OHCI_NEW
121#define CONFIG_SYS_USB_OHCI_CPU_INIT
122#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
123#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
124#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
Bo Shen60f3dd32013-05-12 22:40:54 +0000125#endif
126
Bo Shenf9623df2013-09-11 18:24:51 +0800127/* USB device */
Bo Shenf9623df2013-09-11 18:24:51 +0800128#define CONFIG_USB_ETHER
129#define CONFIG_USB_ETH_RNDIS
130#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK"
131
Bo Shen60f3dd32013-05-12 22:40:54 +0000132#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
Wu, Josha3dd08e2015-01-20 10:33:32 +0800133#define CONFIG_FAT_WRITE
Bo Shen60f3dd32013-05-12 22:40:54 +0000134#endif
135
136#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
137
138#ifdef CONFIG_SYS_USE_SERIALFLASH
Wu, Josh12e84412015-08-19 19:11:21 +0800139/* override the bootcmd, bootargs and other configuration for spi flash env*/
Bo Shen60f3dd32013-05-12 22:40:54 +0000140#elif CONFIG_SYS_USE_NANDFLASH
Wu, Josh244caf02015-08-19 19:11:20 +0800141/* override the bootcmd, bootargs and other configuration nandflash env */
Bo Shen60f3dd32013-05-12 22:40:54 +0000142#elif CONFIG_SYS_USE_MMC
Wu, Josh8b9c7512015-08-19 19:11:18 +0800143/* override the bootcmd, bootargs and other configuration for sd/mmc env */
Bo Shen60f3dd32013-05-12 22:40:54 +0000144#else
Bo Shenadaa1362013-08-11 14:26:20 +0000145#define CONFIG_ENV_IS_NOWHERE
Bo Shen60f3dd32013-05-12 22:40:54 +0000146#endif
147
Bo Shenf92b2982013-11-15 11:12:38 +0800148/* SPL */
Bo Shenf92b2982013-11-15 11:12:38 +0800149#define CONFIG_SPL_FRAMEWORK
150#define CONFIG_SPL_TEXT_BASE 0x300000
151#define CONFIG_SPL_MAX_SIZE 0x10000
152#define CONFIG_SPL_BSS_START_ADDR 0x20000000
153#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
154#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
155#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
156
Bo Shenf92b2982013-11-15 11:12:38 +0800157#define CONFIG_SPL_BOARD_INIT
Bo Shen37a36b32014-03-03 14:47:15 +0800158#define CONFIG_SYS_MONITOR_LEN (512 << 10)
159
Bo Shenf92b2982013-11-15 11:12:38 +0800160#ifdef CONFIG_SYS_USE_MMC
Bo Shen83a718d2015-03-04 13:32:57 +0800161#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
Paul Kocialkowski341e8cd2014-11-08 23:14:55 +0100162#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Guillaume GARDET602a16c2014-10-15 17:53:11 +0200163#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shen37a36b32014-03-03 14:47:15 +0800164
Bo Shen540c0312014-03-03 14:47:17 +0800165#elif CONFIG_SYS_USE_NANDFLASH
Bo Shen540c0312014-03-03 14:47:17 +0800166#define CONFIG_SPL_NAND_DRIVERS
167#define CONFIG_SPL_NAND_BASE
168#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
169#define CONFIG_SYS_NAND_5_ADDR_CYCLE
170#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
171#define CONFIG_SYS_NAND_PAGE_COUNT 64
172#define CONFIG_SYS_NAND_OOBSIZE 64
173#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
174#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
Andreas Bießmannf52c0192014-05-19 14:23:41 +0200175#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
Bo Shen540c0312014-03-03 14:47:17 +0800176
Bo Shen37a36b32014-03-03 14:47:15 +0800177#elif CONFIG_SYS_USE_SERIALFLASH
Bo Shen37a36b32014-03-03 14:47:15 +0800178#define CONFIG_SPL_SPI_LOAD
Wu, Josh12e84412015-08-19 19:11:21 +0800179#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
Bo Shen37a36b32014-03-03 14:47:15 +0800180
Bo Shenf92b2982013-11-15 11:12:38 +0800181#endif
182
Bo Shen60f3dd32013-05-12 22:40:54 +0000183#endif