goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Configuation settings for the Renesas Solutions Migo-R board |
| 3 | * |
| 4 | * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
| 5 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __MIGO_R_H |
| 10 | #define __MIGO_R_H |
| 11 | |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 12 | #define CONFIG_CPU_SH7722 1 |
| 13 | #define CONFIG_MIGO_R 1 |
| 14 | |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 15 | #define CONFIG_CMD_SDRAM |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 16 | |
| 17 | #define CONFIG_BAUDRATE 115200 |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 18 | #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 19 | |
Vladimir Zapolskiy | 5e72b84 | 2016-11-28 00:15:30 +0200 | [diff] [blame] | 20 | #define CONFIG_DISPLAY_BOARDINFO |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 21 | #undef CONFIG_SHOW_BOOT_PROGRESS |
| 22 | |
| 23 | /* SMC9111 */ |
Ben Warren | 0fd6aae | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 24 | #define CONFIG_SMC91111 |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 25 | #define CONFIG_SMC91111_BASE (0xB0000000) |
| 26 | |
| 27 | /* MEMORY */ |
| 28 | #define MIGO_R_SDRAM_BASE (0x8C000000) |
| 29 | #define MIGO_R_FLASH_BASE_1 (0xA0000000) |
| 30 | #define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024) |
| 31 | |
Nobuhiro Iwamatsu | 66a5a38 | 2011-01-17 20:43:40 +0900 | [diff] [blame] | 32 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 33 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 34 | #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ |
| 35 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ |
| 36 | #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ |
| 37 | #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ |
| 38 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 39 | |
| 40 | /* SCIF */ |
Jean-Christophe PLAGNIOL-VILLARD | 6ce9ea6 | 2008-08-13 01:40:38 +0200 | [diff] [blame] | 41 | #define CONFIG_SCIF_CONSOLE 1 |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 42 | #define CONFIG_CONS_SCIF0 1 |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 43 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 44 | #define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE) |
| 45 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 46 | |
| 47 | /* Enable alternate, more extensive, memory test */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 48 | #undef CONFIG_SYS_ALT_MEMTEST |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 49 | /* Scratch address used by the alternate memory test */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 50 | #undef CONFIG_SYS_MEMTEST_SCRATCH |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 51 | |
| 52 | /* Enable temporary baudrate change while serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 53 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 54 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 55 | #define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE) |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 56 | /* maybe more, but if so u-boot doesn't know about it... */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 57 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 58 | /* default load address for scripts ?!? */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 59 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 60 | |
| 61 | /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 62 | #define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1) |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 63 | /* Monitor size */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 64 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 65 | /* Size of DRAM reserved for malloc() use */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 66 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 67 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 68 | |
| 69 | /* FLASH */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 70 | #define CONFIG_SYS_FLASH_CFI |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 71 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 72 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 73 | /* print 'E' for empty sector on flinfo */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 74 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 75 | /* Physical start address of Flash memory */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 76 | #define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1) |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 77 | /* Max number of sectors on each Flash chip */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 78 | #define CONFIG_SYS_MAX_FLASH_SECT 512 |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 79 | |
| 80 | /* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 81 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 82 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) } |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 83 | |
| 84 | /* Timeout for Flash erase operations (in ms) */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 85 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 86 | /* Timeout for Flash write operations (in ms) */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 87 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 88 | /* Timeout for Flash set sector lock bit operations (in ms) */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 89 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 90 | /* Timeout for Flash clear lock bit operations (in ms) */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 91 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 92 | |
| 93 | /* Use hardware flash sectors protection instead of U-Boot software protection */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 94 | #undef CONFIG_SYS_FLASH_PROTECTION |
| 95 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 96 | |
| 97 | /* ENV setting */ |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 98 | #define CONFIG_ENV_IS_IN_FLASH |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 99 | #define CONFIG_ENV_OVERWRITE 1 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 100 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
| 101 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 102 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
| 103 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ |
| 104 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 105 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 106 | |
| 107 | /* Board Clock */ |
| 108 | #define CONFIG_SYS_CLK_FREQ 33333333 |
Nobuhiro Iwamatsu | e698449 | 2013-08-21 16:11:21 +0900 | [diff] [blame] | 109 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
| 110 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
Jean-Christophe PLAGNIOL-VILLARD | 32e6acc | 2009-06-04 12:06:48 +0200 | [diff] [blame] | 111 | #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ |
goda.yusuke | fd76807 | 2008-01-25 20:46:36 +0900 | [diff] [blame] | 112 | |
| 113 | #endif /* __MIGO_R_H */ |