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git01.mediatek.com / filogic / uboot / b7b3637d79c46e07359cf3a89b7902067811a906 / . / arch / sandbox / dts / test.dts
blob: 2c6b42231230a1fe87df8dd15e2bc79494c298ee [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]14 gpio1 = &gpio_a;
15 gpio2 = &gpio_b;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]16 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]17 mmc0 = "/mmc0";
18 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]19 pci0 = &pci0;
20 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]21 pci2 = &pci2;
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]22 remoteproc1 = &rproc_1;
23 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]24 rtc0 = &rtc_0;
25 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]26 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]27 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]28 testbus3 = "/some-bus";
29 testfdt0 = "/some-bus/c-test@0";
30 testfdt1 = "/some-bus/c-test@1";
31 testfdt3 = "/b-test";
32 testfdt5 = "/some-bus/c-test@5";
33 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +0200[diff] [blame]34 fdt-dummy0 = "/translation-test@8000/dev@0,0";
35 fdt-dummy1 = "/translation-test@8000/dev@1,100";
36 fdt-dummy2 = "/translation-test@8000/dev@2,200";
37 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]38 usb0 = &usb_0;
39 usb1 = &usb_1;
40 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]41 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]42 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]43 };
44
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]45 cros_ec: cros-ec {
46 reg = <0 0>;
47 compatible = "google,cros-ec-sandbox";
48
49 /*
50 * This describes the flash memory within the EC. Note
51 * that the STM32L flash erases to 0, not 0xff.
52 */
53 flash {
54 image-pos = <0x08000000>;
55 size = <0x20000>;
56 erase-value = <0>;
57
58 /* Information for sandbox */
59 ro {
60 image-pos = <0>;
61 size = <0xf000>;
62 };
63 wp-ro {
64 image-pos = <0xf000>;
65 size = <0x1000>;
66 };
67 rw {
68 image-pos = <0x10000>;
69 size = <0x10000>;
70 };
71 };
72 };
73
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]74 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]75 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]76 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]77 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]78 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]79 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]80 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
81 <0>, <&gpio_a 12>;
82 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
83 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
84 <&gpio_b 9 0xc 3 2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]85 };
86
87 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]88 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]89 compatible = "not,compatible";
90 };
91
92 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]93 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]94 };
95
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]96 backlight: backlight {
97 compatible = "pwm-backlight";
98 enable-gpios = <&gpio_a 1>;
99 power-supply = <&ldo_1>;
100 pwms = <&pwm 0 1000>;
101 default-brightness-level = <5>;
102 brightness-levels = <0 16 32 64 128 170 202 234 255>;
103 };
104
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200[diff] [blame]105 bind-test {
106 bind-test-child1 {
107 compatible = "sandbox,phy";
108 #phy-cells = <1>;
109 };
110
111 bind-test-child2 {
112 compatible = "simple-bus";
113 };
114 };
115
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]116 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]117 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]118 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]119 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]120 ping-add = <3>;
121 };
122
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200[diff] [blame]123 phy_provider0: gen_phy@0 {
124 compatible = "sandbox,phy";
125 #phy-cells = <1>;
126 };
127
128 phy_provider1: gen_phy@1 {
129 compatible = "sandbox,phy";
130 #phy-cells = <0>;
131 broken;
132 };
133
134 gen_phy_user: gen_phy_user {
135 compatible = "simple-bus";
136 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
137 phy-names = "phy1", "phy2", "phy3";
138 };
139
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]140 some-bus {
141 #address-cells = <1>;
142 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]143 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]144 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]145 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]146 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]147 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]148 compatible = "denx,u-boot-fdt-test";
149 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]150 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]151 ping-add = <5>;
152 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]153 c-test@0 {
154 compatible = "denx,u-boot-fdt-test";
155 reg = <0>;
156 ping-expect = <6>;
157 ping-add = <6>;
158 };
159 c-test@1 {
160 compatible = "denx,u-boot-fdt-test";
161 reg = <1>;
162 ping-expect = <7>;
163 ping-add = <7>;
164 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]165 };
166
167 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]168 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]169 ping-expect = <6>;
170 ping-add = <6>;
171 compatible = "google,another-fdt-test";
172 };
173
174 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]175 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]176 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]177 ping-add = <6>;
178 compatible = "google,another-fdt-test";
179 };
180
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]181 f-test {
182 compatible = "denx,u-boot-fdt-test";
183 };
184
185 g-test {
186 compatible = "denx,u-boot-fdt-test";
187 };
188
Bin Mengd9d24782018-10-10 22:07:01 -0700[diff] [blame]189 h-test {
190 compatible = "denx,u-boot-fdt-test1";
191 };
192
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200[diff] [blame]193 clocks {
194 clk_fixed: clk-fixed {
195 compatible = "fixed-clock";
196 #clock-cells = <0>;
197 clock-frequency = <1234>;
198 };
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]199 };
200
201 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]202 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]203 #clock-cells = <1>;
204 };
205
206 clk-test {
207 compatible = "sandbox,clk-test";
208 clocks = <&clk_fixed>,
209 <&clk_sandbox 1>,
210 <&clk_sandbox 0>;
211 clock-names = "fixed", "i2c", "spi";
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]212 };
213
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]214 eth@10002000 {
215 compatible = "sandbox,eth";
216 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]217 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]218 };
219
220 eth_5: eth@10003000 {
221 compatible = "sandbox,eth";
222 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]223 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]224 };
225
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]226 eth_3: sbe5 {
227 compatible = "sandbox,eth";
228 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]229 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]230 };
231
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]232 eth@10004000 {
233 compatible = "sandbox,eth";
234 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]235 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]236 };
237
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700[diff] [blame]238 firmware {
239 sandbox_firmware: sandbox-firmware {
240 compatible = "sandbox,firmware";
241 };
242 };
243
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]244 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]245 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]246 gpio-controller;
247 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]248 gpio-bank-name = "a";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]249 sandbox,gpio-count = <20>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]250 };
251
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]252 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]253 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]254 gpio-controller;
255 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]256 gpio-bank-name = "b";
Simon Glass9e7ab232018-02-03 10:36:59 -0700[diff] [blame]257 sandbox,gpio-count = <10>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]258 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]259
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]260 i2c@0 {
261 #address-cells = <1>;
262 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]263 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]264 compatible = "sandbox,i2c";
265 clock-frequency = <100000>;
266 eeprom@2c {
267 reg = <0x2c>;
268 compatible = "i2c-eeprom";
269 emul {
270 compatible = "sandbox,i2c-eeprom";
271 sandbox,filename = "i2c.bin";
272 sandbox,size = <256>;
273 };
274 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]275
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]276 rtc_0: rtc@43 {
277 reg = <0x43>;
278 compatible = "sandbox-rtc";
279 emul {
280 compatible = "sandbox,i2c-rtc";
281 };
282 };
283
284 rtc_1: rtc@61 {
285 reg = <0x61>;
286 compatible = "sandbox-rtc";
287 emul {
288 compatible = "sandbox,i2c-rtc";
289 };
290 };
291
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]292 sandbox_pmic: sandbox_pmic {
293 reg = <0x40>;
294 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]295
296 mc34708: pmic@41 {
297 reg = <0x41>;
298 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]299 };
300
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100[diff] [blame]301 adc@0 {
302 compatible = "sandbox,adc";
303 vdd-supply = <&buck2>;
304 vss-microvolts = <0>;
305 };
306
Simon Glass90b6fef2016-01-18 19:52:26 -0700[diff] [blame]307 lcd {
308 u-boot,dm-pre-reloc;
309 compatible = "sandbox,lcd-sdl";
310 xres = <1366>;
311 yres = <768>;
312 };
313
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]314 leds {
315 compatible = "gpio-leds";
316
317 iracibble {
318 gpios = <&gpio_a 1 0>;
319 label = "sandbox:red";
320 };
321
322 martinet {
323 gpios = <&gpio_a 2 0>;
324 label = "sandbox:green";
325 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200[diff] [blame]326
327 default_on {
328 gpios = <&gpio_a 5 0>;
329 label = "sandbox:default_on";
330 default-state = "on";
331 };
332
333 default_off {
334 gpios = <&gpio_a 6 0>;
335 label = "sandbox:default_off";
336 default-state = "off";
337 };
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]338 };
339
Stephen Warren62f2c902016-05-16 17:41:37 -0600[diff] [blame]340 mbox: mbox {
341 compatible = "sandbox,mbox";
342 #mbox-cells = <1>;
343 };
344
345 mbox-test {
346 compatible = "sandbox,mbox-test";
347 mboxes = <&mbox 100>, <&mbox 1>;
348 mbox-names = "other", "test";
349 };
350
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]351 cpu-test1 {
352 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700[diff] [blame]353 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]354 };
355
356 cpu-test2 {
357 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700[diff] [blame]358 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]359 };
360
361 cpu-test3 {
362 compatible = "sandbox,cpu_sandbox";
Bin Mengda3e72f2018-10-14 01:07:20 -0700[diff] [blame]363 u-boot,dm-pre-reloc;
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]364 };
365
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]366 misc-test {
367 compatible = "sandbox,misc_sandbox";
368 };
369
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]370 mmc2 {
371 compatible = "sandbox,mmc";
372 };
373
374 mmc1 {
375 compatible = "sandbox,mmc";
376 };
377
378 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600[diff] [blame]379 compatible = "sandbox,mmc";
380 };
381
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]382 pci0: pci-controller0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]383 compatible = "sandbox,pci";
384 device_type = "pci";
385 #address-cells = <3>;
386 #size-cells = <2>;
387 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
388 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700[diff] [blame]389 pci@0,0 {
390 compatible = "pci-generic";
391 reg = <0x0000 0 0 0 0>;
392 emul@0,0 {
393 compatible = "sandbox,swap-case";
394 };
395 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]396 pci@1f,0 {
397 compatible = "pci-generic";
398 reg = <0xf800 0 0 0 0>;
399 emul@1f,0 {
400 compatible = "sandbox,swap-case";
401 };
402 };
403 };
404
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]405 pci1: pci-controller1 {
406 compatible = "sandbox,pci";
407 device_type = "pci";
408 #address-cells = <3>;
409 #size-cells = <2>;
410 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
411 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700[diff] [blame]412 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200[diff] [blame]413 0x0c 0x00 0x1234 0x5678
414 0x10 0x00 0x1234 0x5678>;
415 pci@10,0 {
416 reg = <0x8000 0 0 0 0>;
417 };
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]418 };
419
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]420 pci2: pci-controller2 {
421 compatible = "sandbox,pci";
422 device_type = "pci";
423 #address-cells = <3>;
424 #size-cells = <2>;
425 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
426 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
427 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
428 pci@1f,0 {
429 compatible = "pci-generic";
430 reg = <0xf800 0 0 0 0>;
431 emul@1f,0 {
432 compatible = "sandbox,swap-case";
433 };
434 };
435 };
436
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]437 probing {
438 compatible = "simple-bus";
439 test1 {
440 compatible = "denx,u-boot-probe-test";
441 };
442
443 test2 {
444 compatible = "denx,u-boot-probe-test";
445 };
446
447 test3 {
448 compatible = "denx,u-boot-probe-test";
449 };
450
451 test4 {
452 compatible = "denx,u-boot-probe-test";
453 };
454 };
455
Stephen Warren92c67fa2016-07-13 13:45:31 -0600[diff] [blame]456 pwrdom: power-domain {
457 compatible = "sandbox,power-domain";
458 #power-domain-cells = <1>;
459 };
460
461 power-domain-test {
462 compatible = "sandbox,power-domain-test";
463 power-domains = <&pwrdom 2>;
464 };
465
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]466 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]467 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]468 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]469 };
470
471 pwm2 {
472 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]473 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]474 };
475
Simon Glass3d355e62015-07-06 12:54:31 -0600[diff] [blame]476 ram {
477 compatible = "sandbox,ram";
478 };
479
Simon Glassd860f222015-07-06 12:54:29 -0600[diff] [blame]480 reset@0 {
481 compatible = "sandbox,warm-reset";
482 };
483
484 reset@1 {
485 compatible = "sandbox,reset";
486 };
487
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]488 resetc: reset-ctl {
489 compatible = "sandbox,reset-ctl";
490 #reset-cells = <1>;
491 };
492
493 reset-ctl-test {
494 compatible = "sandbox,reset-ctl-test";
495 resets = <&resetc 100>, <&resetc 2>;
496 reset-names = "other", "test";
497 };
498
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]499 rproc_1: rproc@1 {
500 compatible = "sandbox,test-processor";
501 remoteproc-name = "remoteproc-test-dev1";
502 };
503
504 rproc_2: rproc@2 {
505 compatible = "sandbox,test-processor";
506 internal-memory-mapped;
507 remoteproc-name = "remoteproc-test-dev2";
508 };
509
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]510 panel {
511 compatible = "simple-panel";
512 backlight = <&backlight 0 100>;
513 };
514
Ramon Fried26ed32e2018-07-02 02:57:59 +0300[diff] [blame]515 smem@0 {
516 compatible = "sandbox,smem";
517 };
518
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]519 spi@0 {
520 #address-cells = <1>;
521 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]522 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]523 compatible = "sandbox,spi";
524 cs-gpios = <0>, <&gpio_a 0>;
525 spi.bin@0 {
526 reg = <0>;
527 compatible = "spansion,m25p16", "spi-flash";
528 spi-max-frequency = <40000000>;
529 sandbox,filename = "spi.bin";
530 };
531 };
532
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]533 syscon@0 {
534 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200[diff] [blame]535 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]536 };
537
538 syscon@1 {
539 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]540 reg = <0x20 5
541 0x28 6
542 0x30 7
543 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]544 };
545
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900[diff] [blame]546 syscon@2 {
547 compatible = "simple-mfd", "syscon";
548 reg = <0x40 5
549 0x48 6
550 0x50 7
551 0x58 8>;
552 };
553
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800[diff] [blame]554 timer {
555 compatible = "sandbox,timer";
556 clock-frequency = <1000000>;
557 };
558
Miquel Raynal80938c12018-05-15 11:57:27 +0200[diff] [blame]559 tpm2 {
560 compatible = "sandbox,tpm2";
561 };
562
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]563 uart0: serial {
564 compatible = "sandbox,serial";
565 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]566 };
567
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]568 usb_0: usb@0 {
569 compatible = "sandbox,usb";
570 status = "disabled";
571 hub {
572 compatible = "sandbox,usb-hub";
573 #address-cells = <1>;
574 #size-cells = <0>;
575 flash-stick {
576 reg = <0>;
577 compatible = "sandbox,usb-flash";
578 };
579 };
580 };
581
582 usb_1: usb@1 {
583 compatible = "sandbox,usb";
584 hub {
585 compatible = "usb-hub";
586 usb,device-class = <9>;
587 hub-emul {
588 compatible = "sandbox,usb-hub";
589 #address-cells = <1>;
590 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]591 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]592 reg = <0>;
593 compatible = "sandbox,usb-flash";
594 sandbox,filepath = "testflash.bin";
595 };
596
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]597 flash-stick@1 {
598 reg = <1>;
599 compatible = "sandbox,usb-flash";
600 sandbox,filepath = "testflash1.bin";
601 };
602
603 flash-stick@2 {
604 reg = <2>;
605 compatible = "sandbox,usb-flash";
606 sandbox,filepath = "testflash2.bin";
607 };
608
Simon Glassc0ccc722015-11-08 23:48:08 -0700[diff] [blame]609 keyb@3 {
610 reg = <3>;
611 compatible = "sandbox,usb-keyb";
612 };
613
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]614 };
615 };
616 };
617
618 usb_2: usb@2 {
619 compatible = "sandbox,usb";
620 status = "disabled";
621 };
622
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]623 spmi: spmi@0 {
624 compatible = "sandbox,spmi";
625 #address-cells = <0x1>;
626 #size-cells = <0x1>;
627 pm8916@0 {
628 compatible = "qcom,spmi-pmic";
629 reg = <0x0 0x1>;
630 #address-cells = <0x1>;
631 #size-cells = <0x1>;
632
633 spmi_gpios: gpios@c000 {
634 compatible = "qcom,pm8916-gpio";
635 reg = <0xc000 0x400>;
636 gpio-controller;
637 gpio-count = <4>;
638 #gpio-cells = <2>;
639 gpio-bank-name="spmi";
640 };
641 };
642 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700[diff] [blame]643
644 wdt0: wdt@0 {
645 compatible = "sandbox,wdt";
646 };
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]647
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]648 axi: axi@0 {
649 compatible = "sandbox,axi";
650 #address-cells = <0x1>;
651 #size-cells = <0x1>;
652 store@0 {
653 compatible = "sandbox,sandbox_store";
654 reg = <0x0 0x400>;
655 };
656 };
657
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]658 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700[diff] [blame]659 #address-cells = <1>;
660 #size-cells = <1>;
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]661 chosen-test {
662 compatible = "denx,u-boot-fdt-test";
663 reg = <9 1>;
664 };
665 };
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]666
667 translation-test@8000 {
668 compatible = "simple-bus";
669 reg = <0x8000 0x4000>;
670
671 #address-cells = <0x2>;
672 #size-cells = <0x1>;
673
674 ranges = <0 0x0 0x8000 0x1000
675 1 0x100 0x9000 0x1000
676 2 0x200 0xA000 0x1000
677 3 0x300 0xB000 0x1000
678 >;
679
680 dev@0,0 {
681 compatible = "denx,u-boot-fdt-dummy";
682 reg = <0 0x0 0x1000>;
683 };
684
685 dev@1,100 {
686 compatible = "denx,u-boot-fdt-dummy";
687 reg = <1 0x100 0x1000>;
688
689 };
690
691 dev@2,200 {
692 compatible = "denx,u-boot-fdt-dummy";
693 reg = <2 0x200 0x1000>;
694 };
695
696
697 noxlatebus@3,300 {
698 compatible = "simple-bus";
699 reg = <3 0x300 0x1000>;
700
701 #address-cells = <0x1>;
702 #size-cells = <0x0>;
703
704 dev@42 {
705 compatible = "denx,u-boot-fdt-dummy";
706 reg = <0x42>;
707 };
708 };
709 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]710
711 osd {
712 compatible = "sandbox,sandbox_osd";
713 };
Tom Rinib93eea72018-09-30 18:16:51 -0400[diff] [blame]714
Mario Sixab664ff2018-07-31 11:44:13 +0200[diff] [blame]715 board {
716 compatible = "sandbox,board_sandbox";
717 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200[diff] [blame]718
719 sandbox_tee {
720 compatible = "sandbox,tee";
721 };
Bin Meng1bb290d2018-10-15 02:21:26 -0700[diff] [blame]722
723 sandbox_virtio1 {
724 compatible = "sandbox,virtio1";
725 };
726
727 sandbox_virtio2 {
728 compatible = "sandbox,virtio2";
729 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200[diff] [blame]730
731 pinctrl {
732 compatible = "sandbox,pinctrl";
733 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]734};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]735
736#include "sandbox_pmic.dtsi"