blob: fca3cddf110e144b90d25890f91b93b431fc4695 [file] [log] [blame]
Poonam Aggrwal987862c2009-08-05 13:29:24 +05301/*
2 * Copyright 2009 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * P1 P2 RDB board configuration file
25 * This file is intended to address a set of Low End and Ultra Low End
26 * Freescale SOCs of QorIQ series(RDB platforms).
27 * Currently only P2020RDB
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
Kumar Gala5b62efc2009-09-10 16:31:53 -050033#ifdef CONFIG_MK_P1011RDB
34#define CONFIG_P1011
35#endif
36#ifdef CONFIG_MK_P1020RDB
37#define CONFIG_P1020
38#endif
39#ifdef CONFIG_MK_P2010RDB
40#define CONFIG_P2010
41#endif
42#ifdef CONFIG_MK_P2020RDB
43#define CONFIG_P2020
44#endif
45
Dipen Dudhate98a3fc2009-10-08 13:33:18 +053046#ifdef CONFIG_MK_NAND
47#define CONFIG_NAND_U_BOOT 1
48#define CONFIG_RAMBOOT_NAND 1
49#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
50#endif
51
Dipen Dudhat529e5fd2009-10-08 13:33:29 +053052#ifdef CONFIG_MK_SDCARD
53#define CONFIG_RAMBOOT_SDCARD 1
54#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
55#endif
56
57#ifdef CONFIG_MK_SPIFLASH
58#define CONFIG_RAMBOOT_SPIFLASH 1
59#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
60#endif
61
Poonam Aggrwal987862c2009-08-05 13:29:24 +053062/* High Level Configuration Options */
63#define CONFIG_BOOKE 1 /* BOOKE */
64#define CONFIG_E500 1 /* BOOKE e500 family */
65#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
66#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
Poonam Aggrwalf857ed92009-08-21 07:29:58 +053067#define CONFIG_PCI 1 /* Enable PCI/PCIE */
68#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
69#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
70#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
71#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
72#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Poonam Aggrwal987862c2009-08-05 13:29:24 +053073#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
74#define CONFIG_TSEC_ENET /* tsec ethernet support */
75#define CONFIG_ENV_OVERWRITE
76
Poonam Aggrwal879e9152010-07-01 14:24:36 +053077#define CONFIG_E1000 1 /* E1000 pci Ethernet card*/
Poonam Aggrwal987862c2009-08-05 13:29:24 +053078#ifndef __ASSEMBLY__
79extern unsigned long get_board_sys_clk(unsigned long dummy);
80#endif
81#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
82#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
83
84#if defined(CONFIG_P2020) || defined(CONFIG_P1020)
85#define CONFIG_MP
86#endif
87
Poonam Aggrwale7502022010-06-23 19:38:06 +053088#define CONFIG_HWCONFIG
89
Poonam Aggrwal987862c2009-08-05 13:29:24 +053090/*
91 * These can be toggled for performance analysis, otherwise use default.
92 */
93#define CONFIG_L2_CACHE /* toggle L2 cache */
94#define CONFIG_BTB /* toggle branch predition */
95
96#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
97
98#define CONFIG_ENABLE_36BIT_PHYS 1
99
100#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
101#define CONFIG_SYS_MEMTEST_END 0x1fffffff
102#define CONFIG_PANIC_HANG /* do not reset board on panic */
103
Dipen Dudhate98a3fc2009-10-08 13:33:18 +0530104 /*
105 * Config the L2 Cache as L2 SRAM
106 */
107#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
108#ifdef CONFIG_PHYS_64BIT
109#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
110#else
111#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
112#endif
113#define CONFIG_SYS_L2_SIZE (512 << 10)
114#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
115
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530116/*
117 * Base addresses -- Note these are effective addresses where the
118 * actual resources get mapped (not physical addresses)
119 */
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530120#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
121#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */
122 /* CCSRBAR */
123#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
124 /* CONFIG_SYS_IMMR */
Dipen Dudhate98a3fc2009-10-08 13:33:18 +0530125
126#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
127#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
128#else
129#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
130#endif
131
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530132/* DDR Setup */
133#define CONFIG_FSL_DDR2
134#undef CONFIG_FSL_DDR_INTERACTIVE
135#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
136#undef CONFIG_DDR_DLL
137
138#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
139
140#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
141#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
142#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
143
144#define CONFIG_NUM_DDR_CONTROLLERS 1
145#define CONFIG_DIMM_SLOTS_PER_CTLR 1
146#define CONFIG_CHIP_SELECTS_PER_CTRL 1
147
148#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
149#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
150#define CONFIG_SYS_DDR_SBE 0x00FF0000
151
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530152/*
153 * Memory map
154 *
155 * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
156 * 0xa000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
157 * 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
158 *
159 * Localbus cacheable (TBD)
160 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
161 *
162 * Localbus non-cacheable
163 * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
164 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
165 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
166 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
167 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
168 */
169
170/*
171 * Local Bus Definitions
172 */
173#define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
174
175#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
176
177#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
178 BR_PS_16 | BR_V)
179#define CONFIG_FLASH_OR_PRELIM 0xff000ff7
180
181#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
182#define CONFIG_SYS_FLASH_QUIET_TEST
183#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
184
185#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
186#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
187#undef CONFIG_SYS_FLASH_CHECKSUM
188#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
189#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
190
191#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
192
Dipen Dudhat529e5fd2009-10-08 13:33:29 +0530193#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
194 || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
Dipen Dudhate98a3fc2009-10-08 13:33:18 +0530195#define CONFIG_SYS_RAMBOOT
196#else
197#undef CONFIG_SYS_RAMBOOT
198#endif
199
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530200#define CONFIG_FLASH_CFI_DRIVER
201#define CONFIG_SYS_FLASH_CFI
202#define CONFIG_SYS_FLASH_EMPTY_INFO
203#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
204
205#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
Vivek Mahajan98306b22010-01-07 14:27:14 +0530206#define CONFIG_HWCONFIG
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530207
208#define CONFIG_SYS_INIT_RAM_LOCK 1
209#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
210#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
211
212#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
213#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
214 - CONFIG_SYS_GBL_DATA_SIZE)
215#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
216
217#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
218#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
219
Dipen Dudhate98a3fc2009-10-08 13:33:18 +0530220#ifndef CONFIG_NAND_SPL
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530221#define CONFIG_SYS_NAND_BASE 0xffa00000
Dipen Dudhate98a3fc2009-10-08 13:33:18 +0530222#else
223#define CONFIG_SYS_NAND_BASE 0xfff00000
224#endif
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530225#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
226#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
227#define CONFIG_SYS_MAX_NAND_DEVICE 1
228#define NAND_MAX_CHIPS 1
229#define CONFIG_MTD_NAND_VERIFY_WRITE
230#define CONFIG_CMD_NAND 1
231#define CONFIG_NAND_FSL_ELBC 1
232#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
233
Dipen Dudhate98a3fc2009-10-08 13:33:18 +0530234/* NAND boot: 4K NAND loader config */
235#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
236#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
237#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
238#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
239#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
240#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
241#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
242
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530243/* NAND flash config */
244#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
245 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
246 | BR_PS_8 /* Port Size = 8 bit */ \
247 | BR_MS_FCM /* MSEL = FCM */ \
248 | BR_V) /* valid */
249
250#define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
251 | OR_FCM_CSCT \
252 | OR_FCM_CST \
253 | OR_FCM_CHT \
254 | OR_FCM_SCY_1 \
255 | OR_FCM_TRLX \
256 | OR_FCM_EHTR)
257
Dipen Dudhate98a3fc2009-10-08 13:33:18 +0530258#ifdef CONFIG_RAMBOOT_NAND
259#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
260#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
261#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
262#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
263#else
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530264#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
265#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
266#define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
267#define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Dipen Dudhate98a3fc2009-10-08 13:33:18 +0530268#endif
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530269
270#define CONFIG_SYS_VSC7385_BASE 0xffb00000
271
272#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
273
274#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
275#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
276 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
277 OR_GPCM_EHTR | OR_GPCM_EAD)
278
279/* Serial Port - controlled on board with jumper J8
280 * open - index 2
281 * shorted - index 1
282 */
283#define CONFIG_CONS_INDEX 1
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530284#undef CONFIG_SERIAL_SOFTWARE_FIFO
285#define CONFIG_SYS_NS16550
286#define CONFIG_SYS_NS16550_SERIAL
287#define CONFIG_SYS_NS16550_REG_SIZE 1
288#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Galaf2736232010-04-07 01:34:11 -0500289#ifdef CONFIG_NAND_SPL
290#define CONFIG_NS16550_MIN_FUNCTIONS
291#endif
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530292
293#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
294#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
295
296#define CONFIG_SYS_BAUDRATE_TABLE \
297 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
298
299#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
300#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
301
302/* Use the HUSH parser */
303#define CONFIG_SYS_HUSH_PARSER
304#ifdef CONFIG_SYS_HUSH_PARSER
305#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
306#endif
307
308/*
309 * Pass open firmware flat tree
310 */
311#define CONFIG_OF_LIBFDT 1
312#define CONFIG_OF_BOARD_SETUP 1
313#define CONFIG_OF_STDOUT_VIA_ALIAS 1
314
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530315/* new uImage format support */
316#define CONFIG_FIT 1
317#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
318
319/* I2C */
320#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
321#define CONFIG_HARD_I2C /* I2C with hardware support */
322#undef CONFIG_SOFT_I2C /* I2C bit-banged */
323#define CONFIG_I2C_MULTI_BUS
324#define CONFIG_I2C_CMD_TREE
325#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
326#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
327#define CONFIG_SYS_I2C_SLAVE 0x7F
328#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
329#define CONFIG_SYS_I2C_OFFSET 0x3000
330#define CONFIG_SYS_I2C2_OFFSET 0x3100
331
332/*
333 * I2C2 EEPROM
334 */
335#define CONFIG_ID_EEPROM
336#ifdef CONFIG_ID_EEPROM
337#define CONFIG_SYS_I2C_EEPROM_NXID
338#endif
339#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
340#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
341#define CONFIG_SYS_EEPROM_BUS_NUM 1
342
343#define CONFIG_RTC_DS1337
344#define CONFIG_SYS_I2C_RTC_ADDR 0x68
345/*
346 * General PCI
347 * Memory space is mapped 1-1, but I/O space must start from 0.
348 */
349
350/* controller 2, Slot 2, tgtid 2, Base address 9000 */
351#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
352#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
353#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
354#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
355#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
356#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
357#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
358#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
359
360/* controller 1, Slot 1, tgtid 1, Base address a000 */
361#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
362#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
363#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
364#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
365#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
366#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
367#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
368#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
369
370#if defined(CONFIG_PCI)
371#define CONFIG_NET_MULTI
372#define CONFIG_PCI_PNP /* do pci plug-and-play */
373
374#undef CONFIG_EEPRO100
375#undef CONFIG_TULIP
376#undef CONFIG_RTL8139
377
378#ifdef CONFIG_RTL8139
379/* This macro is used by RTL8139 but not defined in PPC architecture */
380#define KSEG1ADDR(x) (x)
381#define _IO_BASE 0x00000000
382#endif
383
384
385#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
386#define CONFIG_DOS_PARTITION
387
388#endif /* CONFIG_PCI */
389
390#if defined(CONFIG_TSEC_ENET)
391#ifndef CONFIG_NET_MULTI
392#define CONFIG_NET_MULTI 1
393#endif
394
395#define CONFIG_MII 1 /* MII PHY management */
396#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
397#define CONFIG_TSEC1 1
398#define CONFIG_TSEC1_NAME "eTSEC1"
399#define CONFIG_TSEC2 1
400#define CONFIG_TSEC2_NAME "eTSEC2"
401#define CONFIG_TSEC3 1
402#define CONFIG_TSEC3_NAME "eTSEC3"
403
404#define TSEC1_PHY_ADDR 2
405#define TSEC2_PHY_ADDR 0
406#define TSEC3_PHY_ADDR 1
407
408#define CONFIG_VSC7385_ENET
409
410#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
411#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
412#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
413
414#define TSEC1_PHYIDX 0
415#define TSEC2_PHYIDX 0
416#define TSEC3_PHYIDX 0
417
418/* Vitesse 7385 */
419
420#ifdef CONFIG_VSC7385_ENET
421/* The size of the VSC7385 firmware image */
422#define CONFIG_VSC7385_IMAGE_SIZE 8192
423#endif
424
425#define CONFIG_ETHPRIME "eTSEC1"
426
427#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Felix Radensky27f98e02010-06-28 01:57:39 +0300428
429/* TBI PHY configuration for SGMII mode */
430#define CONFIG_TSEC_TBICR_SETTINGS ( \
431 TBICR_PHY_RESET \
432 | TBICR_ANEG_ENABLE \
433 | TBICR_FULL_DUPLEX \
434 | TBICR_SPEED1_SET \
435 )
436
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530437#endif /* CONFIG_TSEC_ENET */
438
439/*
440 * Environment
441 */
Dipen Dudhate98a3fc2009-10-08 13:33:18 +0530442#if defined(CONFIG_SYS_RAMBOOT)
443#if defined(CONFIG_RAMBOOT_NAND)
444 #define CONFIG_ENV_IS_IN_NAND 1
445 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
446 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
Dipen Dudhat529e5fd2009-10-08 13:33:29 +0530447#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
448 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
449 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
450 #define CONFIG_ENV_SIZE 0x2000
Dipen Dudhate98a3fc2009-10-08 13:33:18 +0530451#endif
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530452#else
Dipen Dudhate98a3fc2009-10-08 13:33:18 +0530453 #define CONFIG_ENV_IS_IN_FLASH 1
454 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
455 #define CONFIG_ENV_ADDR 0xfff80000
456 #else
457 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
458 #endif
459 #define CONFIG_ENV_SIZE 0x2000
460 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530461#endif
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530462
463#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
464#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
465
466/*
467 * Command line configuration.
468 */
469#include <config_cmd_default.h>
470
471#define CONFIG_CMD_DATE
472#define CONFIG_CMD_ELF
473#define CONFIG_CMD_I2C
474#define CONFIG_CMD_IRQ
475#define CONFIG_CMD_MII
476#define CONFIG_CMD_PING
477#define CONFIG_CMD_SETEXPR
Becky Bruceee888da2010-06-17 11:37:25 -0500478#define CONFIG_CMD_REGINFO
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530479
480#if defined(CONFIG_PCI)
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530481#define CONFIG_CMD_NET
482#define CONFIG_CMD_PCI
483#endif
484
485#undef CONFIG_WATCHDOG /* watchdog disabled */
486
487#define CONFIG_MMC 1
488
489#ifdef CONFIG_MMC
490#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
491#define CONFIG_CMD_MMC
492#define CONFIG_DOS_PARTITION
493#define CONFIG_FSL_ESDHC
494#define CONFIG_GENERIC_MMC
495#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
496#ifdef CONFIG_P2020
497#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
498#endif
499#endif
500
501#define CONFIG_USB_EHCI
502
503#ifdef CONFIG_USB_EHCI
504#define CONFIG_CMD_USB
505#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
506#define CONFIG_USB_EHCI_FSL
507#define CONFIG_USB_STORAGE
508#endif
509
510#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
511#define CONFIG_CMD_EXT2
512#define CONFIG_CMD_FAT
513#define CONFIG_DOS_PARTITION
514#endif
515
516/*
517 * Miscellaneous configurable options
518 */
519#define CONFIG_SYS_LONGHELP /* undef to save memory */
520#define CONFIG_CMDLINE_EDITING /* Command-line editing */
521#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
522#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
523#if defined(CONFIG_CMD_KGDB)
524#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
525#else
526#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
527#endif
528#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
529 /* Print Buffer Size */
530#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
531#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
532#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
533
534/*
535 * For booting Linux, the board info and command line data
536 * have to be in the first 16 MB of memory, since this is
537 * the maximum mapped by the Linux kernel during initialization.
538 */
539#define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/
540
541/*
542 * Internal Definitions
543 *
544 * Boot Flags
545 */
546#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
547#define BOOTFLAG_WARM 0x02 /* Software reboot */
548
549#if defined(CONFIG_CMD_KGDB)
550#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
551#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
552#endif
553
554/*
555 * Environment Configuration
556 */
557
558#if defined(CONFIG_TSEC_ENET)
559#define CONFIG_HAS_ETH0
560#define CONFIG_HAS_ETH1
561#define CONFIG_HAS_ETH2
562#endif
563
564#define CONFIG_HOSTNAME P2020RDB
565#define CONFIG_ROOTPATH /opt/nfsroot
566#define CONFIG_BOOTFILE uImage
567#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
568
569/* default location for tftp and bootm */
570#define CONFIG_LOADADDR 1000000
571
572#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
573#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
574
575#define CONFIG_BAUDRATE 115200
576
577#define CONFIG_EXTRA_ENV_SETTINGS \
578 "netdev=eth0\0" \
579 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
580 "loadaddr=1000000\0" \
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530581 "tftpflash=tftpboot $loadaddr $uboot; " \
582 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
583 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
584 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
585 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
586 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
587 "consoledev=ttyS0\0" \
588 "ramdiskaddr=2000000\0" \
589 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
590 "fdtaddr=c00000\0" \
591 "fdtfile=p2020rdb.dtb\0" \
592 "bdev=sda1\0" \
593 "jffs2nor=mtdblock3\0" \
594 "norbootaddr=ef080000\0" \
595 "norfdtaddr=ef040000\0" \
596 "jffs2nand=mtdblock9\0" \
597 "nandbootaddr=100000\0" \
598 "nandfdtaddr=80000\0" \
599 "nandimgsize=400000\0" \
600 "nandfdtsize=80000\0" \
601 "usb_phy_type=ulpi\0" \
602 "vscfw_addr=ef000000\0" \
603 "othbootargs=ramdisk_size=600000\0" \
604 "usbfatboot=setenv bootargs root=/dev/ram rw " \
605 "console=$consoledev,$baudrate $othbootargs; " \
606 "usb start;" \
607 "fatload usb 0:2 $loadaddr $bootfile;" \
608 "fatload usb 0:2 $fdtaddr $fdtfile;" \
609 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
610 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
611 "usbext2boot=setenv bootargs root=/dev/ram rw " \
612 "console=$consoledev,$baudrate $othbootargs; " \
613 "usb start;" \
614 "ext2load usb 0:4 $loadaddr $bootfile;" \
615 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
616 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
617 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
618 "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
619 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
620 "bootm $norbootaddr - $norfdtaddr\0" \
621 "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
622 "console=$consoledev,$baudrate $othbootargs;" \
623 "nand read 2000000 $nandbootaddr $nandimgsize;" \
624 "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
625 "bootm 2000000 - 3000000;\0"
626
627#define CONFIG_NFSBOOTCOMMAND \
628 "setenv bootargs root=/dev/nfs rw " \
629 "nfsroot=$serverip:$rootpath " \
630 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
631 "console=$consoledev,$baudrate $othbootargs;" \
632 "tftp $loadaddr $bootfile;" \
633 "tftp $fdtaddr $fdtfile;" \
634 "bootm $loadaddr - $fdtaddr"
635
636#define CONFIG_HDBOOT \
637 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
638 "console=$consoledev,$baudrate $othbootargs;" \
639 "usb start;" \
640 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
641 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
642 "bootm $loadaddr - $fdtaddr"
643
644#define CONFIG_RAMBOOTCOMMAND \
645 "setenv bootargs root=/dev/ram rw " \
646 "console=$consoledev,$baudrate $othbootargs; " \
647 "tftp $ramdiskaddr $ramdiskfile;" \
648 "tftp $loadaddr $bootfile;" \
649 "tftp $fdtaddr $fdtfile;" \
650 "bootm $loadaddr $ramdiskaddr $fdtaddr"
651
652#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
653
654#endif /* __CONFIG_H */