dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 1 | /* |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 2 | * (C) Copyright 2003-2004 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * (C) Copyright 2004 |
| 6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
| 7 | * |
| 8 | * (C) Copyright 2004-2005 |
| 9 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
| 10 | * |
| 11 | * (C) Copyright 2006 |
| 12 | * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de |
| 13 | * |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 14 | * See file CREDITS for list of people who contributed to this |
| 15 | * project. |
| 16 | * |
| 17 | * This program is free software; you can redistribute it and/or |
| 18 | * modify it under the terms of the GNU General Public License as |
| 19 | * published by the Free Software Foundation; either version 2 of |
| 20 | * the License, or (at your option) any later version. |
| 21 | * |
| 22 | * This program is distributed in the hope that it will be useful, |
| 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 25 | * GNU General Public License for more details. |
| 26 | * |
| 27 | * You should have received a copy of the GNU General Public License |
| 28 | * along with this program; if not, write to the Free Software |
| 29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 30 | * MA 02111-1307 USA |
| 31 | */ |
| 32 | |
| 33 | #include <common.h> |
| 34 | #include <mpc5xxx.h> |
| 35 | #include <pci.h> |
Ben Warren | f2c1acb | 2008-08-31 10:03:22 -0700 | [diff] [blame] | 36 | #include <netdev.h> |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 37 | |
| 38 | #ifdef CONFIG_VIDEO_SM501 |
| 39 | #include <sm501.h> |
| 40 | #endif |
| 41 | |
| 42 | #if defined(CONFIG_MPC5200_DDR) |
| 43 | #include "mt46v16m16-75.h" |
| 44 | #else |
| 45 | #include "mt48lc16m16a2-75.h" |
| 46 | #endif |
| 47 | |
| 48 | #ifdef CONFIG_RTC_MPC5200 |
| 49 | #include <rtc.h> |
Wolfgang Denk | a846799 | 2006-05-03 01:24:04 +0200 | [diff] [blame] | 50 | #endif |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 51 | |
| 52 | #ifdef CONFIG_PS2MULT |
| 53 | void ps2mult_early_init(void); |
| 54 | #endif |
| 55 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 56 | #ifndef CONFIG_SYS_RAMBOOT |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 57 | static void sdram_start (int hi_addr) |
| 58 | { |
| 59 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
| 60 | |
| 61 | /* unlock mode register */ |
| 62 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | |
| 63 | hi_addr_bit; |
| 64 | __asm__ volatile ("sync"); |
| 65 | |
| 66 | /* precharge all banks */ |
| 67 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | |
| 68 | hi_addr_bit; |
| 69 | __asm__ volatile ("sync"); |
| 70 | |
| 71 | #if SDRAM_DDR |
| 72 | /* set mode register: extended mode */ |
| 73 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; |
| 74 | __asm__ volatile ("sync"); |
| 75 | |
| 76 | /* set mode register: reset DLL */ |
| 77 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; |
| 78 | __asm__ volatile ("sync"); |
| 79 | #endif |
| 80 | |
| 81 | /* precharge all banks */ |
| 82 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | |
| 83 | hi_addr_bit; |
| 84 | __asm__ volatile ("sync"); |
| 85 | |
| 86 | /* auto refresh */ |
| 87 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | |
| 88 | hi_addr_bit; |
| 89 | __asm__ volatile ("sync"); |
| 90 | |
| 91 | /* set mode register */ |
| 92 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; |
| 93 | __asm__ volatile ("sync"); |
| 94 | |
| 95 | /* normal operation */ |
| 96 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; |
| 97 | __asm__ volatile ("sync"); |
| 98 | } |
| 99 | #endif |
| 100 | |
| 101 | /* |
| 102 | * ATTENTION: Although partially referenced initdram does NOT make real use |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 103 | * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 104 | * is something else than 0x00000000. |
| 105 | */ |
| 106 | |
Becky Bruce | bd99ae7 | 2008-06-09 16:03:40 -0500 | [diff] [blame] | 107 | phys_size_t initdram (int board_type) |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 108 | { |
| 109 | ulong dramsize = 0; |
| 110 | ulong dramsize2 = 0; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 111 | #ifndef CONFIG_SYS_RAMBOOT |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 112 | ulong test1, test2; |
| 113 | |
| 114 | /* setup SDRAM chip selects */ |
| 115 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ |
| 116 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ |
| 117 | __asm__ volatile ("sync"); |
| 118 | |
| 119 | /* setup config registers */ |
| 120 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
| 121 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; |
| 122 | __asm__ volatile ("sync"); |
| 123 | |
| 124 | #if SDRAM_DDR |
| 125 | /* set tap delay */ |
| 126 | *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; |
| 127 | __asm__ volatile ("sync"); |
| 128 | #endif |
| 129 | |
| 130 | /* find RAM size using SDRAM CS0 only */ |
| 131 | sdram_start(0); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 132 | test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 133 | sdram_start(1); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 134 | test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 135 | if (test1 > test2) { |
| 136 | sdram_start(0); |
| 137 | dramsize = test1; |
| 138 | } else { |
| 139 | dramsize = test2; |
| 140 | } |
| 141 | |
| 142 | /* memory smaller than 1MB is impossible */ |
| 143 | if (dramsize < (1 << 20)) { |
| 144 | dramsize = 0; |
| 145 | } |
| 146 | |
| 147 | /* set SDRAM CS0 size according to the amount of RAM found */ |
| 148 | if (dramsize > 0) { |
| 149 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + |
| 150 | __builtin_ffs(dramsize >> 20) - 1; |
| 151 | } else { |
| 152 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ |
| 153 | } |
| 154 | |
| 155 | /* let SDRAM CS1 start right after CS0 */ |
| 156 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */ |
| 157 | |
| 158 | /* find RAM size using SDRAM CS1 only */ |
| 159 | sdram_start(0); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 160 | test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 161 | sdram_start(1); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 162 | test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 163 | if (test1 > test2) { |
| 164 | sdram_start(0); |
| 165 | dramsize2 = test1; |
| 166 | } else { |
| 167 | dramsize2 = test2; |
| 168 | } |
| 169 | |
| 170 | /* memory smaller than 1MB is impossible */ |
| 171 | if (dramsize2 < (1 << 20)) { |
| 172 | dramsize2 = 0; |
| 173 | } |
| 174 | |
| 175 | /* set SDRAM CS1 size according to the amount of RAM found */ |
| 176 | if (dramsize2 > 0) { |
| 177 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize |
| 178 | | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); |
| 179 | } else { |
| 180 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ |
| 181 | } |
| 182 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 183 | #else /* CONFIG_SYS_RAMBOOT */ |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 184 | |
| 185 | /* retrieve size of memory connected to SDRAM CS0 */ |
| 186 | dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; |
| 187 | if (dramsize >= 0x13) { |
| 188 | dramsize = (1 << (dramsize - 0x13)) << 20; |
| 189 | } else { |
| 190 | dramsize = 0; |
| 191 | } |
| 192 | |
| 193 | /* retrieve size of memory connected to SDRAM CS1 */ |
| 194 | dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; |
| 195 | if (dramsize2 >= 0x13) { |
| 196 | dramsize2 = (1 << (dramsize2 - 0x13)) << 20; |
| 197 | } else { |
| 198 | dramsize2 = 0; |
| 199 | } |
| 200 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 201 | #endif /* CONFIG_SYS_RAMBOOT */ |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 202 | |
| 203 | return dramsize; |
| 204 | } |
| 205 | |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 206 | int checkboard (void) |
| 207 | { |
| 208 | #if defined (CONFIG_TQM5200) |
| 209 | puts ("Board: TQM5200 (TQ-Components GmbH)\n"); |
| 210 | #endif |
| 211 | |
| 212 | #if defined (CONFIG_BC3450) |
| 213 | puts ("Dev: GERSYS BC3450\n"); |
| 214 | #endif |
| 215 | |
| 216 | return 0; |
| 217 | } |
| 218 | |
| 219 | void flash_preinit(void) |
| 220 | { |
| 221 | /* |
| 222 | * Now, when we are in RAM, enable flash write |
| 223 | * access for detection process. |
| 224 | * Note that CS_BOOT cannot be cleared when |
| 225 | * executing in flash. |
| 226 | */ |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 227 | *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ |
| 228 | } |
| 229 | |
| 230 | |
| 231 | #ifdef CONFIG_PCI |
| 232 | static struct pci_controller hose; |
| 233 | |
| 234 | extern void pci_mpc5xxx_init(struct pci_controller *); |
| 235 | |
| 236 | void pci_init_board(void) |
| 237 | { |
| 238 | pci_mpc5xxx_init(&hose); |
| 239 | } |
| 240 | #endif |
| 241 | |
Jon Loeliger | 13f7599 | 2007-07-10 10:39:10 -0500 | [diff] [blame] | 242 | #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 243 | |
| 244 | void init_ide_reset (void) |
| 245 | { |
| 246 | debug ("init_ide_reset\n"); |
| 247 | |
| 248 | /* Configure PSC1_4 as GPIO output for ATA reset */ |
| 249 | *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; |
| 250 | *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; |
| 251 | } |
| 252 | |
| 253 | void ide_set_reset (int idereset) |
| 254 | { |
| 255 | debug ("ide_reset(%d)\n", idereset); |
| 256 | |
| 257 | if (idereset) { |
Bartlomiej Sieka | 79eecbfb | 2006-11-01 01:38:16 +0100 | [diff] [blame] | 258 | *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 259 | } else { |
Bartlomiej Sieka | 79eecbfb | 2006-11-01 01:38:16 +0100 | [diff] [blame] | 260 | *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 261 | } |
| 262 | } |
Jon Loeliger | 13f7599 | 2007-07-10 10:39:10 -0500 | [diff] [blame] | 263 | #endif |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 264 | |
| 265 | #ifdef CONFIG_POST |
| 266 | /* |
| 267 | * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 |
| 268 | * is left open, no keypress is detected. |
| 269 | */ |
| 270 | int post_hotkeys_pressed(void) |
| 271 | { |
| 272 | struct mpc5xxx_gpio *gpio; |
| 273 | |
| 274 | gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO; |
| 275 | |
| 276 | /* |
| 277 | * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in |
| 278 | * CODEC or UART mode. Consumer IrDA should still be possible. |
| 279 | */ |
| 280 | gpio->port_config &= ~(0x07000000); |
| 281 | gpio->port_config |= 0x03000000; |
| 282 | |
| 283 | /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ |
| 284 | gpio->simple_gpioe |= 0x20000000; |
| 285 | |
| 286 | /* Configure GPIO_IRDA_1 as input */ |
| 287 | gpio->simple_ddr &= ~(0x20000000); |
| 288 | |
| 289 | return ((gpio->simple_ival & 0x20000000) ? 0 : 1); |
| 290 | } |
| 291 | #endif |
| 292 | |
| 293 | #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) |
| 294 | |
| 295 | void post_word_store (ulong a) |
| 296 | { |
| 297 | volatile ulong *save_addr = |
| 298 | (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); |
| 299 | |
| 300 | *save_addr = a; |
| 301 | } |
| 302 | |
| 303 | ulong post_word_load (void) |
| 304 | { |
| 305 | volatile ulong *save_addr = |
| 306 | (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); |
| 307 | |
| 308 | return *save_addr; |
| 309 | } |
| 310 | #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ |
| 311 | |
| 312 | |
| 313 | #ifdef CONFIG_BOARD_EARLY_INIT_R |
| 314 | int board_early_init_r (void) |
| 315 | { |
| 316 | #ifdef CONFIG_RTC_MPC5200 |
Wolfgang Denk | a846799 | 2006-05-03 01:24:04 +0200 | [diff] [blame] | 317 | struct rtc_time t; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 318 | |
| 319 | /* set to Wed Dec 31 19:00:00 1969 */ |
| 320 | t.tm_sec = t.tm_min = 0; |
| 321 | t.tm_hour = 19; |
| 322 | t.tm_mday = 31; |
| 323 | t.tm_mon = 12; |
| 324 | t.tm_year = 1969; |
| 325 | t.tm_wday = 3; |
Wolfgang Denk | a846799 | 2006-05-03 01:24:04 +0200 | [diff] [blame] | 326 | |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 327 | rtc_set(&t); |
| 328 | #endif /* CONFIG_RTC_MPC5200 */ |
| 329 | |
| 330 | #ifdef CONFIG_PS2MULT |
| 331 | ps2mult_early_init(); |
| 332 | #endif /* CONFIG_PS2MULT */ |
| 333 | return (0); |
| 334 | } |
| 335 | #endif /* CONFIG_BOARD_EARLY_INIT_R */ |
| 336 | |
| 337 | |
| 338 | int last_stage_init (void) |
| 339 | { |
| 340 | /* |
| 341 | * auto scan for really existing devices and re-set chip select |
| 342 | * configuration. |
| 343 | */ |
| 344 | u16 save, tmp; |
| 345 | int restore; |
| 346 | |
| 347 | /* |
| 348 | * Check for SRAM and SRAM size |
| 349 | */ |
| 350 | |
| 351 | /* save original SRAM content */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 352 | save = *(volatile u16 *)CONFIG_SYS_CS2_START; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 353 | restore = 1; |
| 354 | |
| 355 | /* write test pattern to SRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 356 | *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 357 | __asm__ volatile ("sync"); |
| 358 | /* |
| 359 | * Put a different pattern on the data lines: otherwise they may float |
| 360 | * long enough to read back what we wrote. |
| 361 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 362 | tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 363 | if (tmp == 0xA5A5) |
| 364 | puts ("!! possible error in SRAM detection\n"); |
| 365 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 366 | if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) { |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 367 | /* no SRAM at all, disable cs */ |
| 368 | *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); |
| 369 | *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; |
| 370 | *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; |
| 371 | restore = 0; |
| 372 | __asm__ volatile ("sync"); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 373 | } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) { |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 374 | /* make sure that we access a mirrored address */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 375 | *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 376 | __asm__ volatile ("sync"); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 377 | if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) { |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 378 | /* SRAM size = 512 kByte */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 379 | *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 380 | 0x80000); |
| 381 | __asm__ volatile ("sync"); |
| 382 | puts ("SRAM: 512 kB\n"); |
| 383 | } |
| 384 | else |
| 385 | puts ("!! possible error in SRAM detection\n"); |
| 386 | } else { |
| 387 | puts ("SRAM: 1 MB\n"); |
| 388 | } |
| 389 | /* restore origianl SRAM content */ |
| 390 | if (restore) { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 391 | *(volatile u16 *)CONFIG_SYS_CS2_START = save; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 392 | __asm__ volatile ("sync"); |
| 393 | } |
| 394 | |
| 395 | /* |
| 396 | * Check for Grafic Controller |
| 397 | */ |
| 398 | |
| 399 | /* save origianl FB content */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 400 | save = *(volatile u16 *)CONFIG_SYS_CS1_START; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 401 | restore = 1; |
| 402 | |
| 403 | /* write test pattern to FB memory */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 404 | *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 405 | __asm__ volatile ("sync"); |
| 406 | /* |
| 407 | * Put a different pattern on the data lines: otherwise they may float |
| 408 | * long enough to read back what we wrote. |
| 409 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 410 | tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 411 | if (tmp == 0xA5A5) |
| 412 | puts ("!! possible error in grafic controller detection\n"); |
| 413 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 414 | if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 415 | /* no grafic controller at all, disable cs */ |
| 416 | *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); |
| 417 | *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; |
| 418 | *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF; |
| 419 | restore = 0; |
| 420 | __asm__ volatile ("sync"); |
| 421 | } else { |
| 422 | puts ("VGA: SMI501 (Voyager) with 8 MB\n"); |
| 423 | } |
Wolfgang Denk | a846799 | 2006-05-03 01:24:04 +0200 | [diff] [blame] | 424 | /* restore origianl FB content */ |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 425 | if (restore) { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 426 | *(volatile u16 *)CONFIG_SYS_CS1_START = save; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 427 | __asm__ volatile ("sync"); |
| 428 | } |
| 429 | |
| 430 | return 0; |
| 431 | } |
| 432 | |
| 433 | #ifdef CONFIG_VIDEO_SM501 |
| 434 | |
Wolfgang Denk | a846799 | 2006-05-03 01:24:04 +0200 | [diff] [blame] | 435 | #define DISPLAY_WIDTH 640 |
| 436 | #define DISPLAY_HEIGHT 480 |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 437 | |
| 438 | #ifdef CONFIG_VIDEO_SM501_8BPP |
| 439 | #error CONFIG_VIDEO_SM501_8BPP not supported. |
| 440 | #endif /* CONFIG_VIDEO_SM501_8BPP */ |
| 441 | |
| 442 | #ifdef CONFIG_VIDEO_SM501_16BPP |
| 443 | #error CONFIG_VIDEO_SM501_16BPP not supported. |
| 444 | #endif /* CONFIG_VIDEO_SM501_16BPP */ |
| 445 | |
| 446 | #ifdef CONFIG_VIDEO_SM501_32BPP |
| 447 | static const SMI_REGS init_regs [] = |
| 448 | { |
| 449 | #if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT) |
| 450 | /* FP only */ |
| 451 | {0x00004, 0x0}, |
| 452 | {0x00048, 0x00021807}, |
| 453 | {0x0004C, 0x091a0a01}, |
| 454 | {0x00054, 0x1}, |
| 455 | {0x00040, 0x00021807}, |
| 456 | {0x00044, 0x091a0a01}, |
| 457 | {0x00054, 0x0}, |
| 458 | {0x80000, 0x01013106}, |
| 459 | {0x80004, 0xc428bb17}, |
| 460 | {0x80000, 0x03013106}, |
| 461 | {0x8000C, 0x00000000}, |
| 462 | {0x80010, 0x0a000a00}, |
| 463 | {0x80014, 0x02800000}, |
| 464 | {0x80018, 0x01e00000}, |
| 465 | {0x8001C, 0x00000000}, |
| 466 | {0x80020, 0x01e00280}, |
| 467 | {0x80024, 0x02fa027f}, |
| 468 | {0x80028, 0x004a028b}, |
| 469 | {0x8002C, 0x020c01df}, |
| 470 | {0x80030, 0x000201e9}, |
| 471 | {0x80200, 0x00010200}, |
| 472 | {0x80000, 0x0f013106}, |
| 473 | #elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP) |
| 474 | /* CRT only */ |
| 475 | {0x00004, 0x0}, |
| 476 | {0x00048, 0x00021807}, |
| 477 | {0x0004C, 0x10090a01}, |
| 478 | {0x00054, 0x1}, |
| 479 | {0x00040, 0x00021807}, |
| 480 | {0x00044, 0x10090a01}, |
| 481 | {0x00054, 0x0}, |
| 482 | {0x80200, 0x00010000}, |
| 483 | {0x80204, 0x0}, |
| 484 | {0x80208, 0x0A000A00}, |
| 485 | {0x8020C, 0x02fa027f}, |
| 486 | {0x80210, 0x004a028b}, |
| 487 | {0x80214, 0x020c01df}, |
| 488 | {0x80218, 0x000201e9}, |
| 489 | {0x80200, 0x00013306}, |
| 490 | #else /* panel + CRT */ |
| 491 | {0x00004, 0x0}, |
| 492 | {0x00048, 0x00021807}, |
| 493 | {0x0004C, 0x091a0a01}, |
| 494 | {0x00054, 0x1}, |
| 495 | {0x00040, 0x00021807}, |
| 496 | {0x00044, 0x091a0a01}, |
| 497 | {0x00054, 0x0}, |
| 498 | {0x80000, 0x0f013106}, |
| 499 | {0x80004, 0xc428bb17}, |
| 500 | {0x8000C, 0x00000000}, |
| 501 | {0x80010, 0x0a000a00}, |
| 502 | {0x80014, 0x02800000}, |
| 503 | {0x80018, 0x01e00000}, |
| 504 | {0x8001C, 0x00000000}, |
| 505 | {0x80020, 0x01e00280}, |
| 506 | {0x80024, 0x02fa027f}, |
| 507 | {0x80028, 0x004a028b}, |
| 508 | {0x8002C, 0x020c01df}, |
| 509 | {0x80030, 0x000201e9}, |
| 510 | {0x80200, 0x00010000}, |
| 511 | #endif |
| 512 | {0, 0} |
| 513 | }; |
| 514 | #endif /* CONFIG_VIDEO_SM501_32BPP */ |
| 515 | |
| 516 | #ifdef CONFIG_CONSOLE_EXTRA_INFO |
| 517 | /* |
| 518 | * Return text to be printed besides the logo. |
| 519 | */ |
| 520 | void video_get_info_str (int line_number, char *info) |
| 521 | { |
| 522 | if (line_number == 1) { |
| 523 | #if defined (CONFIG_TQM5200) |
| 524 | strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); |
| 525 | #else |
| 526 | #error No supported board selected |
| 527 | #endif /* CONFIG_TQM5200 */ |
| 528 | |
| 529 | #if defined (CONFIG_BC3450) |
| 530 | } else if (line_number == 2) { |
| 531 | strcpy (info, " Dev: GERSYS BC3450"); |
| 532 | #endif /* CONFIG_BC3450 */ |
| 533 | } |
| 534 | else { |
| 535 | info [0] = '\0'; |
| 536 | } |
| 537 | } |
| 538 | #endif |
| 539 | |
| 540 | /* |
| 541 | * Returns SM501 register base address. First thing called in the |
| 542 | * driver. Checks if SM501 is physically present. |
| 543 | */ |
| 544 | unsigned int board_video_init (void) |
| 545 | { |
| 546 | u16 save, tmp; |
| 547 | int restore, ret; |
| 548 | |
| 549 | /* |
| 550 | * Check for Grafic Controller |
| 551 | */ |
| 552 | |
| 553 | /* save origianl FB content */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 554 | save = *(volatile u16 *)CONFIG_SYS_CS1_START; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 555 | restore = 1; |
| 556 | |
| 557 | /* write test pattern to FB memory */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 558 | *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 559 | __asm__ volatile ("sync"); |
| 560 | /* |
| 561 | * Put a different pattern on the data lines: otherwise they may float |
| 562 | * long enough to read back what we wrote. |
| 563 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 564 | tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 565 | if (tmp == 0xA5A5) |
| 566 | puts ("!! possible error in grafic controller detection\n"); |
| 567 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 568 | if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 569 | /* no grafic controller found */ |
| 570 | restore = 0; |
| 571 | ret = 0; |
| 572 | } else { |
| 573 | ret = SM501_MMIO_BASE; |
| 574 | } |
Wolfgang Denk | a846799 | 2006-05-03 01:24:04 +0200 | [diff] [blame] | 575 | |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 576 | if (restore) { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 577 | *(volatile u16 *)CONFIG_SYS_CS1_START = save; |
dzu@denx.de | c59e4ac | 2006-04-21 18:30:47 +0200 | [diff] [blame] | 578 | __asm__ volatile ("sync"); |
| 579 | } |
| 580 | return ret; |
| 581 | } |
| 582 | |
| 583 | /* |
| 584 | * Returns SM501 framebuffer address |
| 585 | */ |
| 586 | unsigned int board_video_get_fb (void) |
| 587 | { |
| 588 | return SM501_FB_BASE; |
| 589 | } |
| 590 | |
| 591 | /* |
| 592 | * Called after initializing the SM501 and before clearing the screen. |
| 593 | */ |
| 594 | void board_validate_screen (unsigned int base) |
| 595 | { |
| 596 | } |
| 597 | |
| 598 | /* |
| 599 | * Return a pointer to the initialization sequence. |
| 600 | */ |
| 601 | const SMI_REGS *board_get_regs (void) |
| 602 | { |
| 603 | return init_regs; |
| 604 | } |
| 605 | |
| 606 | int board_get_width (void) |
| 607 | { |
| 608 | return DISPLAY_WIDTH; |
| 609 | } |
| 610 | |
| 611 | int board_get_height (void) |
| 612 | { |
| 613 | return DISPLAY_HEIGHT; |
| 614 | } |
| 615 | |
| 616 | #endif /* CONFIG_VIDEO_SM501 */ |
Ben Warren | f2c1acb | 2008-08-31 10:03:22 -0700 | [diff] [blame] | 617 | |
| 618 | int board_eth_init(bd_t *bis) |
| 619 | { |
Ben Warren | cba8851 | 2008-08-31 10:39:12 -0700 | [diff] [blame] | 620 | cpu_eth_init(bis); /* Built in FEC comes first */ |
Ben Warren | f2c1acb | 2008-08-31 10:03:22 -0700 | [diff] [blame] | 621 | return pci_eth_init(bis); |
| 622 | } |