blob: 52c2a9f24d7902ee73355b285548cb5447591701 [file] [log] [blame]
Patrick Delaunay8e34fbb2022-05-20 18:24:39 +02001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
5 */
6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8&pinctrl {
Marek Vasut726f6342024-04-28 00:20:37 +02009 adc1_pins_a: adc1-pins-0 {
10 pins {
11 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
12 };
13 };
14
Patrick Delaunay7f2cba42023-04-24 16:21:10 +020015 adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
16 pins {
17 pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
18 <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
19 };
20 };
21
Marek Vasut726f6342024-04-28 00:20:37 +020022 adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
23 pins {
24 pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */
25 <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */
26 };
27 };
28
29 eth1_rgmii_pins_a: eth1-rgmii-0 {
30 pins1 {
31 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
32 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
33 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
34 <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */
35 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
36 <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */
37 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
38 <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
39 bias-disable;
40 drive-push-pull;
41 slew-rate = <2>;
42 };
43
44 pins2 {
45 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
46 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
47 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
48 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
49 <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */
50 <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */
51 bias-disable;
52 };
53
54 };
55
56 eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
57 pins1 {
58 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
59 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
60 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
61 <STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */
62 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
63 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */
64 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
65 <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
66 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
67 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
68 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */
69 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */
70 <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */
71 <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */
72 };
73 };
74
75 eth2_rgmii_pins_a: eth2-rgmii-0 {
76 pins1 {
77 pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */
78 <STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */
79 <STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */
80 <STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */
81 <STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */
82 <STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */
83 <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */
84 <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
85 bias-disable;
86 drive-push-pull;
87 slew-rate = <2>;
88 };
89
90 pins2 {
91 pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */
92 <STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */
93 <STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */
94 <STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */
95 <STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */
96 <STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */
97 bias-disable;
98 };
99 };
100
101 eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
102 pins1 {
103 pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
104 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */
105 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD2 */
106 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
107 <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RGMII_TX_CTL */
108 <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_GTX_CLK */
109 <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
110 <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
111 <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
112 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
113 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD2 */
114 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD3 */
115 <STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */
116 <STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */
117 };
118 };
119
Patrick Delaunay7f2cba42023-04-24 16:21:10 +0200120 i2c1_pins_a: i2c1-0 {
121 pins {
122 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
123 <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
124 bias-disable;
125 drive-open-drain;
126 slew-rate = <0>;
127 };
128 };
129
130 i2c1_sleep_pins_a: i2c1-sleep-0 {
131 pins {
132 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
133 <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
134 };
135 };
136
137 i2c5_pins_a: i2c5-0 {
138 pins {
139 pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
140 <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
141 bias-disable;
142 drive-open-drain;
143 slew-rate = <0>;
144 };
145 };
146
147 i2c5_sleep_pins_a: i2c5-sleep-0 {
148 pins {
149 pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
150 <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
151 };
152 };
153
Marek Vasut726f6342024-04-28 00:20:37 +0200154 i2c5_pins_b: i2c5-1 {
155 pins {
156 pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
157 <STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */
158 bias-disable;
159 drive-open-drain;
160 slew-rate = <0>;
161 };
162 };
163
164 i2c5_sleep_pins_b: i2c5-sleep-1 {
165 pins {
166 pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
167 <STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */
168 };
169 };
170
171 m_can1_pins_a: m-can1-0 {
172 pins1 {
173 pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */
174 slew-rate = <1>;
175 drive-push-pull;
176 bias-disable;
177 };
178 pins2 {
179 pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
180 bias-disable;
181 };
182 };
183
184 m_can1_sleep_pins_a: m_can1-sleep-0 {
185 pins {
186 pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */
187 <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */
188 };
189 };
190
191 m_can2_pins_a: m-can2-0 {
192 pins1 {
193 pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */
194 slew-rate = <1>;
195 drive-push-pull;
196 bias-disable;
197 };
198 pins2 {
199 pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */
200 bias-disable;
201 };
202 };
203
204 m_can2_sleep_pins_a: m_can2-sleep-0 {
205 pins {
206 pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */
207 <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */
208 };
209 };
210
Patrick Delaunay7f2cba42023-04-24 16:21:10 +0200211 mcp23017_pins_a: mcp23017-0 {
212 pins {
213 pinmux = <STM32_PINMUX('G', 12, GPIO)>;
214 bias-pull-up;
215 };
216 };
217
Cheick Traore1455c0c2025-03-11 15:30:37 +0100218 pwm1_ch3n_pins_a: pwm1-ch3n-0 {
219 pins {
220 pinmux = <STM32_PINMUX('E', 12, AF1)>; /* TIM1_CH3N */
221 bias-pull-down;
222 drive-push-pull;
223 slew-rate = <0>;
224 };
225 };
226
227 pwm1_ch3n_sleep_pins_a: pwm1-ch3n-sleep-0 {
228 pins {
229 pinmux = <STM32_PINMUX('E', 12, ANALOG)>; /* TIM1_CH3N */
230 };
231 };
232
Patrick Delaunay7f2cba42023-04-24 16:21:10 +0200233 pwm3_pins_a: pwm3-0 {
234 pins {
235 pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
236 bias-pull-down;
237 drive-push-pull;
238 slew-rate = <0>;
239 };
240 };
241
242 pwm3_sleep_pins_a: pwm3-sleep-0 {
243 pins {
244 pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
245 };
246 };
247
248 pwm4_pins_a: pwm4-0 {
249 pins {
250 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
251 bias-pull-down;
252 drive-push-pull;
253 slew-rate = <0>;
254 };
255 };
256
257 pwm4_sleep_pins_a: pwm4-sleep-0 {
258 pins {
259 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
260 };
261 };
262
Marek Vasut726f6342024-04-28 00:20:37 +0200263 pwm5_pins_a: pwm5-0 {
264 pins {
265 pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */
266 bias-pull-down;
267 drive-push-pull;
268 slew-rate = <0>;
269 };
270 };
271
272 pwm5_sleep_pins_a: pwm5-sleep-0 {
273 pins {
274 pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */
275 };
276 };
277
Patrick Delaunay7f2cba42023-04-24 16:21:10 +0200278 pwm8_pins_a: pwm8-0 {
279 pins {
280 pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
281 bias-pull-down;
282 drive-push-pull;
283 slew-rate = <0>;
284 };
285 };
286
287 pwm8_sleep_pins_a: pwm8-sleep-0 {
288 pins {
289 pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
290 };
291 };
292
Marek Vasut726f6342024-04-28 00:20:37 +0200293 pwm13_pins_a: pwm13-0 {
294 pins {
295 pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */
296 bias-pull-down;
297 drive-push-pull;
298 slew-rate = <0>;
299 };
300 };
301
302 pwm13_sleep_pins_a: pwm13-sleep-0 {
303 pins {
304 pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */
305 };
306 };
307
Patrick Delaunay7f2cba42023-04-24 16:21:10 +0200308 pwm14_pins_a: pwm14-0 {
309 pins {
310 pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
311 bias-pull-down;
312 drive-push-pull;
313 slew-rate = <0>;
314 };
315 };
316
317 pwm14_sleep_pins_a: pwm14-sleep-0 {
318 pins {
319 pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
320 };
321 };
322
Marek Vasut726f6342024-04-28 00:20:37 +0200323 qspi_clk_pins_a: qspi-clk-0 {
324 pins {
325 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
326 bias-disable;
327 drive-push-pull;
328 slew-rate = <3>;
329 };
330 };
331
332 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
333 pins {
334 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
335 };
336 };
337
338 qspi_bk1_pins_a: qspi-bk1-0 {
339 pins {
340 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
341 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
342 <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */
343 <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */
344 bias-disable;
345 drive-push-pull;
346 slew-rate = <1>;
347 };
348 };
349
350 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
351 pins {
352 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
353 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
354 <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */
355 <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */
356 };
357 };
358
359 qspi_cs1_pins_a: qspi-cs1-0 {
360 pins {
361 pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */
362 bias-pull-up;
363 drive-push-pull;
364 slew-rate = <1>;
365 };
366 };
367
368 qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
369 pins {
370 pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */
371 };
372 };
373
374 sai1a_pins_a: sai1a-0 {
375 pins {
376 pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
377 <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */
378 <STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */
379 slew-rate = <0>;
380 drive-push-pull;
381 bias-disable;
382 };
383 };
384
385 sai1a_sleep_pins_a: sai1a-sleep-0 {
386 pins {
387 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
388 <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */
389 <STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */
390 };
391 };
392
393 sai1b_pins_a: sai1b-0 {
394 pins {
395 pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */
396 bias-disable;
397 };
398 };
399
400 sai1b_sleep_pins_a: sai1b-sleep-0 {
401 pins {
402 pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */
403 };
404 };
405
Patrick Delaunay8e34fbb2022-05-20 18:24:39 +0200406 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
407 pins {
408 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
409 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
410 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
411 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
412 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
413 slew-rate = <1>;
414 drive-push-pull;
415 bias-disable;
416 };
417 };
418
419 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
420 pins1 {
421 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
422 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
423 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
424 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
425 slew-rate = <1>;
426 drive-push-pull;
427 bias-disable;
428 };
429 pins2 {
430 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
431 slew-rate = <1>;
432 drive-open-drain;
433 bias-disable;
434 };
435 };
436
437 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
438 pins {
439 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
440 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
441 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
442 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
443 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
444 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
445 };
446 };
447
448 sdmmc1_clk_pins_a: sdmmc1-clk-0 {
449 pins {
450 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
451 slew-rate = <1>;
452 drive-push-pull;
453 bias-disable;
454 };
455 };
456
457 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
458 pins {
459 pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
460 <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
461 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
462 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
463 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
464 slew-rate = <1>;
465 drive-push-pull;
466 bias-pull-up;
467 };
468 };
469
470 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
471 pins1 {
472 pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
473 <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
474 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
475 <STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */
476 slew-rate = <1>;
477 drive-push-pull;
478 bias-pull-up;
479 };
480 pins2 {
481 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
482 slew-rate = <1>;
483 drive-open-drain;
484 bias-pull-up;
485 };
486 };
487
488 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
489 pins {
490 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
491 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
492 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
493 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
494 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
495 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
496 };
497 };
498
499 sdmmc2_clk_pins_a: sdmmc2-clk-0 {
500 pins {
501 pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
502 slew-rate = <1>;
503 drive-push-pull;
504 bias-pull-up;
505 };
506 };
507
Marek Vasut726f6342024-04-28 00:20:37 +0200508 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
509 pins {
510 pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
511 <STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
512 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
513 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
514 slew-rate = <1>;
515 drive-push-pull;
516 bias-pull-up;
517 };
518 };
519
520 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
521 pins {
522 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */
523 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */
524 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
525 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
526 };
527 };
528
529 spi2_pins_a: spi2-0 {
530 pins1 {
531 pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */
532 <STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */
533 bias-disable;
534 drive-push-pull;
535 slew-rate = <1>;
536 };
537
538 pins2 {
539 pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */
540 bias-disable;
541 };
542 };
543
544 spi2_sleep_pins_a: spi2-sleep-0 {
545 pins {
546 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */
547 <STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */
548 <STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */
549 };
550 };
551
552 spi3_pins_a: spi3-0 {
553 pins1 {
554 pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */
555 <STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */
556 bias-disable;
557 drive-push-pull;
558 slew-rate = <1>;
559 };
560
561 pins2 {
562 pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */
563 bias-disable;
564 };
565 };
566
567 spi3_sleep_pins_a: spi3-sleep-0 {
568 pins {
569 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */
570 <STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */
571 <STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */
572 };
573 };
574
Patrick Delaunay7f2cba42023-04-24 16:21:10 +0200575 spi5_pins_a: spi5-0 {
576 pins1 {
577 pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
578 <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */
579 bias-disable;
580 drive-push-pull;
581 slew-rate = <1>;
582 };
583
584 pins2 {
585 pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
586 bias-disable;
587 };
588 };
589
590 spi5_sleep_pins_a: spi5-sleep-0 {
591 pins {
592 pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
593 <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
594 <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */
595 };
596 };
597
598 stm32g0_intn_pins_a: stm32g0-intn-0 {
599 pins {
600 pinmux = <STM32_PINMUX('I', 2, GPIO)>;
601 bias-pull-up;
602 };
603 };
604
Patrick Delaunay8e34fbb2022-05-20 18:24:39 +0200605 uart4_pins_a: uart4-0 {
606 pins1 {
607 pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
608 bias-disable;
609 drive-push-pull;
610 slew-rate = <0>;
611 };
612 pins2 {
613 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
614 bias-disable;
615 };
616 };
Patrick Delaunay4597d262023-07-10 10:38:45 +0200617
618 uart4_idle_pins_a: uart4-idle-0 {
619 pins1 {
620 pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
621 };
622 pins2 {
623 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
624 bias-disable;
625 };
626 };
627
628 uart4_sleep_pins_a: uart4-sleep-0 {
629 pins {
630 pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
631 <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
632 };
633 };
634
Marek Vasut726f6342024-04-28 00:20:37 +0200635 uart4_pins_b: uart4-1 {
636 pins1 {
637 pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */
638 bias-disable;
639 drive-push-pull;
640 slew-rate = <0>;
641 };
642 pins2 {
643 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
644 bias-pull-up;
645 };
646 };
647
648 uart4_idle_pins_b: uart4-idle-1 {
649 pins1 {
650 pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */
651 };
652 pins2 {
653 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
654 bias-pull-up;
655 };
656 };
657
658 uart4_sleep_pins_b: uart4-sleep-1 {
659 pins {
660 pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */
661 <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
662 };
663 };
664
665 uart7_pins_a: uart7-0 {
666 pins1 {
667 pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */
668 <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
669 bias-disable;
670 drive-push-pull;
671 slew-rate = <0>;
672 };
673 pins2 {
674 pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */
675 <STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */
676 bias-disable;
677 };
678 };
679
680 uart7_idle_pins_a: uart7-idle-0 {
681 pins1 {
682 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
683 <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
684 };
685 pins2 {
686 pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
687 bias-disable;
688 drive-push-pull;
689 slew-rate = <0>;
690 };
691 pins3 {
692 pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */
693 bias-disable;
694 };
695 };
696
697 uart7_sleep_pins_a: uart7-sleep-0 {
698 pins {
699 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
700 <STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */
701 <STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */
702 <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
703 };
704 };
705
Patrick Delaunay4597d262023-07-10 10:38:45 +0200706 uart8_pins_a: uart8-0 {
707 pins1 {
708 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
709 bias-disable;
710 drive-push-pull;
711 slew-rate = <0>;
712 };
713 pins2 {
714 pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
715 bias-pull-up;
716 };
717 };
718
719 uart8_idle_pins_a: uart8-idle-0 {
720 pins1 {
721 pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
722 };
723 pins2 {
724 pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
725 bias-pull-up;
726 };
727 };
728
729 uart8_sleep_pins_a: uart8-sleep-0 {
730 pins {
731 pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
732 <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
733 };
734 };
735
736 usart1_pins_a: usart1-0 {
737 pins1 {
738 pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
739 <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
740 bias-disable;
741 drive-push-pull;
742 slew-rate = <0>;
743 };
744 pins2 {
745 pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
746 <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
747 bias-pull-up;
748 };
749 };
750
751 usart1_idle_pins_a: usart1-idle-0 {
752 pins1 {
753 pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
754 <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
755 };
756 pins2 {
757 pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
758 bias-disable;
759 drive-push-pull;
760 slew-rate = <0>;
761 };
762 pins3 {
763 pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
764 bias-pull-up;
765 };
766 };
767
768 usart1_sleep_pins_a: usart1-sleep-0 {
769 pins {
770 pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
771 <STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
772 <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
773 <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
774 };
775 };
776
Marek Vasut726f6342024-04-28 00:20:37 +0200777 usart1_pins_b: usart1-1 {
778 pins1 {
779 pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */
780 bias-disable;
781 drive-push-pull;
782 slew-rate = <0>;
783 };
784 pins2 {
785 pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
786 bias-pull-up;
787 };
788 };
789
790 usart1_idle_pins_b: usart1-idle-1 {
791 pins1 {
792 pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */
793 };
794 pins2 {
795 pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
796 bias-pull-up;
797 };
798 };
799
800 usart1_sleep_pins_b: usart1-sleep-1 {
801 pins {
802 pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
803 <STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */
804 };
805 };
806
Patrick Delaunay4597d262023-07-10 10:38:45 +0200807 usart2_pins_a: usart2-0 {
808 pins1 {
809 pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
810 <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
811 bias-disable;
812 drive-push-pull;
813 slew-rate = <0>;
814 };
815 pins2 {
816 pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
817 <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
818 bias-disable;
819 };
820 };
821
822 usart2_idle_pins_a: usart2-idle-0 {
823 pins1 {
824 pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
825 <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
826 };
827 pins2 {
828 pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
829 bias-disable;
830 drive-push-pull;
831 slew-rate = <0>;
832 };
833 pins3 {
834 pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
835 bias-disable;
836 };
837 };
838
839 usart2_sleep_pins_a: usart2-sleep-0 {
840 pins {
841 pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
842 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
843 <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
844 <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
845 };
846 };
Marek Vasut726f6342024-04-28 00:20:37 +0200847
848 usart2_pins_b: usart2-0 {
849 pins1 {
850 pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */
851 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
852 bias-disable;
853 drive-push-pull;
854 slew-rate = <0>;
855 };
856 pins2 {
857 pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
858 <STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */
859 bias-disable;
860 };
861 };
862
863 usart2_idle_pins_b: usart2-idle-0 {
864 pins1 {
865 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
866 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
867 };
868 pins2 {
869 pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
870 bias-disable;
871 drive-push-pull;
872 slew-rate = <0>;
873 };
874 pins3 {
875 pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
876 bias-disable;
877 };
878 };
879
880 usart2_sleep_pins_b: usart2-sleep-0 {
881 pins {
882 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
883 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
884 <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
885 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
886 };
887 };
Patrick Delaunay8e34fbb2022-05-20 18:24:39 +0200888};