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git01.mediatek.com / filogic / uboot / b781f5756999b8bb3b4e592141d1dd45bca113ff / . / board / amcc / canyonlands / chip_config.c
blob: e48557098f81a1ee20e7cd8d2ebe076600dc50b5 [file] [log] [blame]
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]1/*
2 * (C) Copyright 2008-2009
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]6 */
7
8#include <common.h>
9#include <asm/ppc4xx_config.h>
10
11struct ppc4xx_config ppc4xx_config_val[] = {
12 {
13 "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
14 {
15 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
16 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
17 }
18 },
19 {
Stefan Roesefce070a2009-08-17 16:57:53 +0200[diff] [blame]20 "800-nor", "NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100",
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]21 {
Stefan Roesefce070a2009-08-17 16:57:53 +0200[diff] [blame]22 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
23 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]24 }
25 },
26 {
Stefan Roesefce070a2009-08-17 16:57:53 +0200[diff] [blame]27 "1000-nor", "NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100",
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]28 {
Stefan Roesefce070a2009-08-17 16:57:53 +0200[diff] [blame]29 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]30 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
31 }
32 },
33 {
Stefan Roesefce070a2009-08-17 16:57:53 +0200[diff] [blame]34 "1066-nor", "NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88",
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]35 {
Stefan Roesefce070a2009-08-17 16:57:53 +0200[diff] [blame]36 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
37 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]38 }
39 },
Stefan Roesefce070a2009-08-17 16:57:53 +0200[diff] [blame]40#if !defined(CONFIG_ARCHES)
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]41 {
Stefan Roesefce070a2009-08-17 16:57:53 +0200[diff] [blame]42 "600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]43 {
Stefan Roesefce070a2009-08-17 16:57:53 +0200[diff] [blame]44 0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
45 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]46 }
47 },
48 {
Stefan Roesefce070a2009-08-17 16:57:53 +0200[diff] [blame]49 "800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]50 {
Stefan Roesefce070a2009-08-17 16:57:53 +0200[diff] [blame]51 0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]52 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
53 }
54 },
55 {
Stefan Roesefce070a2009-08-17 16:57:53 +0200[diff] [blame]56 "1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]57 {
Stefan Roesefce070a2009-08-17 16:57:53 +0200[diff] [blame]58 0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
59 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]60 }
61 },
62 {
63 "1066-nand", "NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88",
64 {
65 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0,
66 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
67 }
68 },
Stefan Roesefce070a2009-08-17 16:57:53 +0200[diff] [blame]69#endif
Stefan Roese9693c3d2009-07-20 06:57:27 +0200[diff] [blame]70};
71
72int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);