Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Vikas Manocha | 5dba05e | 2016-02-11 15:47:19 -0800 | [diff] [blame] | 2 | /* |
Patrice Chotard | 789ee0e | 2017-10-23 09:53:58 +0200 | [diff] [blame] | 3 | * Copyright (C) 2016, STMicroelectronics - All Rights Reserved |
| 4 | * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. |
Vikas Manocha | 5dba05e | 2016-02-11 15:47:19 -0800 | [diff] [blame] | 5 | */ |
| 6 | |
Patrice Chotard | 9e27650 | 2018-01-12 09:23:49 +0100 | [diff] [blame] | 7 | #ifndef _SERIAL_STM32_ |
| 8 | #define _SERIAL_STM32_ |
Vikas Manocha | 5dba05e | 2016-02-11 15:47:19 -0800 | [diff] [blame] | 9 | |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 10 | #include <linux/bitops.h> |
Patrice Chotard | 5011e6f | 2017-09-27 15:44:50 +0200 | [diff] [blame] | 11 | #define CR1_OFFSET(x) (x ? 0x0c : 0x00) |
| 12 | #define CR3_OFFSET(x) (x ? 0x14 : 0x08) |
| 13 | #define BRR_OFFSET(x) (x ? 0x08 : 0x0c) |
| 14 | #define ISR_OFFSET(x) (x ? 0x00 : 0x1c) |
Patrice Chotard | 24af24b | 2018-04-20 08:59:06 +0200 | [diff] [blame] | 15 | |
| 16 | #define ICR_OFFSET 0x20 |
Patrick Delaunay | 39ffe0e | 2018-05-17 14:50:45 +0200 | [diff] [blame] | 17 | |
Patrice Chotard | 5011e6f | 2017-09-27 15:44:50 +0200 | [diff] [blame] | 18 | /* |
| 19 | * STM32F4 has one Data Register (DR) for received or transmitted |
| 20 | * data, so map Receive Data Register (RDR) and Transmit Data |
| 21 | * Register (TDR) at the same offset |
| 22 | */ |
| 23 | #define RDR_OFFSET(x) (x ? 0x04 : 0x24) |
| 24 | #define TDR_OFFSET(x) (x ? 0x04 : 0x28) |
| 25 | |
| 26 | struct stm32_uart_info { |
| 27 | u8 uart_enable_bit; /* UART_CR1_UE */ |
| 28 | bool stm32f4; /* true for STM32F4, false otherwise */ |
Patrice Chotard | 24fc72d | 2017-09-27 15:44:51 +0200 | [diff] [blame] | 29 | bool has_fifo; |
Patrice Chotard | 5011e6f | 2017-09-27 15:44:50 +0200 | [diff] [blame] | 30 | }; |
| 31 | |
Patrice Chotard | b21a69a | 2017-09-27 15:44:52 +0200 | [diff] [blame] | 32 | struct stm32_uart_info stm32f4_info = { |
| 33 | .stm32f4 = true, |
| 34 | .uart_enable_bit = 13, |
Patrice Chotard | b21a69a | 2017-09-27 15:44:52 +0200 | [diff] [blame] | 35 | .has_fifo = false, |
| 36 | }; |
| 37 | |
Patrice Chotard | 24fc72d | 2017-09-27 15:44:51 +0200 | [diff] [blame] | 38 | struct stm32_uart_info stm32f7_info = { |
Patrice Chotard | 5011e6f | 2017-09-27 15:44:50 +0200 | [diff] [blame] | 39 | .uart_enable_bit = 0, |
| 40 | .stm32f4 = false, |
Patrice Chotard | 988de86 | 2018-09-20 15:14:15 +0200 | [diff] [blame] | 41 | .has_fifo = true, |
Vikas Manocha | 5dba05e | 2016-02-11 15:47:19 -0800 | [diff] [blame] | 42 | }; |
| 43 | |
Patrice Chotard | 24fc72d | 2017-09-27 15:44:51 +0200 | [diff] [blame] | 44 | struct stm32_uart_info stm32h7_info = { |
| 45 | .uart_enable_bit = 0, |
| 46 | .stm32f4 = false, |
Patrice Chotard | 24fc72d | 2017-09-27 15:44:51 +0200 | [diff] [blame] | 47 | .has_fifo = true, |
| 48 | }; |
| 49 | |
Patrice Chotard | 2195315 | 2017-07-18 09:29:07 +0200 | [diff] [blame] | 50 | /* Information about a serial port */ |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame^] | 51 | struct stm32x7_serial_plat { |
Patrice Chotard | 5011e6f | 2017-09-27 15:44:50 +0200 | [diff] [blame] | 52 | fdt_addr_t base; /* address of registers in physical memory */ |
| 53 | struct stm32_uart_info *uart_info; |
Patrice Chotard | 4809a19 | 2017-07-18 09:29:08 +0200 | [diff] [blame] | 54 | unsigned long int clock_rate; |
Patrice Chotard | 2195315 | 2017-07-18 09:29:07 +0200 | [diff] [blame] | 55 | }; |
Vikas Manocha | 5dba05e | 2016-02-11 15:47:19 -0800 | [diff] [blame] | 56 | |
Patrice Chotard | 24fc72d | 2017-09-27 15:44:51 +0200 | [diff] [blame] | 57 | #define USART_CR1_FIFOEN BIT(29) |
Patrick Delaunay | 39ffe0e | 2018-05-17 14:50:45 +0200 | [diff] [blame] | 58 | #define USART_CR1_M1 BIT(28) |
Patrice Chotard | 6961a9d | 2017-09-27 15:44:48 +0200 | [diff] [blame] | 59 | #define USART_CR1_OVER8 BIT(15) |
Patrick Delaunay | 39ffe0e | 2018-05-17 14:50:45 +0200 | [diff] [blame] | 60 | #define USART_CR1_M0 BIT(12) |
| 61 | #define USART_CR1_PCE BIT(10) |
| 62 | #define USART_CR1_PS BIT(9) |
Patrice Chotard | 6961a9d | 2017-09-27 15:44:48 +0200 | [diff] [blame] | 63 | #define USART_CR1_TE BIT(3) |
| 64 | #define USART_CR1_RE BIT(2) |
Vikas Manocha | 5dba05e | 2016-02-11 15:47:19 -0800 | [diff] [blame] | 65 | |
Patrice Chotard | 6961a9d | 2017-09-27 15:44:48 +0200 | [diff] [blame] | 66 | #define USART_CR3_OVRDIS BIT(12) |
Vikas Manocha | 59535d5 | 2017-05-28 12:55:12 -0700 | [diff] [blame] | 67 | |
Patrice Chotard | db0536e | 2018-05-17 14:50:43 +0200 | [diff] [blame] | 68 | #define USART_ISR_TXE BIT(7) |
| 69 | #define USART_ISR_RXNE BIT(5) |
| 70 | #define USART_ISR_ORE BIT(3) |
Patrick Delaunay | 1a103bf | 2019-07-30 19:16:46 +0200 | [diff] [blame] | 71 | #define USART_ISR_FE BIT(1) |
Patrick Delaunay | 39ffe0e | 2018-05-17 14:50:45 +0200 | [diff] [blame] | 72 | #define USART_ISR_PE BIT(0) |
Vikas Manocha | 5dba05e | 2016-02-11 15:47:19 -0800 | [diff] [blame] | 73 | |
Patrice Chotard | 6961a9d | 2017-09-27 15:44:48 +0200 | [diff] [blame] | 74 | #define USART_BRR_F_MASK GENMASK(7, 0) |
Vikas Manocha | 5dba05e | 2016-02-11 15:47:19 -0800 | [diff] [blame] | 75 | #define USART_BRR_M_SHIFT 4 |
Patrice Chotard | 6961a9d | 2017-09-27 15:44:48 +0200 | [diff] [blame] | 76 | #define USART_BRR_M_MASK GENMASK(15, 4) |
Vikas Manocha | 5dba05e | 2016-02-11 15:47:19 -0800 | [diff] [blame] | 77 | |
Patrice Chotard | db0536e | 2018-05-17 14:50:43 +0200 | [diff] [blame] | 78 | #define USART_ICR_ORECF BIT(3) |
Patrick Delaunay | 1a103bf | 2019-07-30 19:16:46 +0200 | [diff] [blame] | 79 | #define USART_ICR_FECF BIT(1) |
Patrick Delaunay | 39ffe0e | 2018-05-17 14:50:45 +0200 | [diff] [blame] | 80 | #define USART_ICR_PCECF BIT(0) |
| 81 | |
Vikas Manocha | 5dba05e | 2016-02-11 15:47:19 -0800 | [diff] [blame] | 82 | #endif |