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git01.mediatek.com / filogic / uboot / b6fad961b39da2ff1d35f920c384558df15d4386 / . / arch / arm / mach-versal / mp.c
blob: 2487b482ddb15a6ce5d12622aada083eef13c600 [file] [log] [blame]
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * (C) Copyright 2019 Xilinx, Inc.
Michal Simek7359cc22023-09-22 12:35:35 +0200[diff] [blame]4 * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]5 */
6
7#include <common.h>
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]8#include <asm/io.h>
9#include <asm/arch/hardware.h>
10#include <asm/arch/sys_proto.h>
11
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]12#define HALT 0
13#define RELEASE 1
14
15#define VERSAL_RPU_CFG_CPU_HALT_MASK 0x01
16#define VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK 0x08
17#define VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK 0x40
18#define VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK 0x10
19
20#define VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK 0x04
21#define VERSAL_CRLAPB_RST_LPD_R50_RST_MASK 0x01
22#define VERSAL_CRLAPB_RST_LPD_R51_RST_MASK 0x02
23#define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10
24#define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000
25
Algapally Santosh Sagarb0142c12023-06-09 03:05:31 -0600[diff] [blame]26static void set_r5_halt_mode(u8 halt, u8 mode)
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]27{
28 u32 tmp;
29
30 tmp = readl(&rpu_base->rpu0_cfg);
31 if (halt == HALT)
32 tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK;
33 else
34 tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK;
35 writel(tmp, &rpu_base->rpu0_cfg);
36
37 if (mode == TCM_LOCK) {
38 tmp = readl(&rpu_base->rpu1_cfg);
39 if (halt == HALT)
40 tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK;
41 else
42 tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK;
43 writel(tmp, &rpu_base->rpu1_cfg);
44 }
45}
46
Algapally Santosh Sagarb0142c12023-06-09 03:05:31 -0600[diff] [blame]47static void set_r5_tcm_mode(u8 mode)
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]48{
49 u32 tmp;
50
51 tmp = readl(&rpu_base->rpu_glbl_ctrl);
52 if (mode == TCM_LOCK) {
53 tmp &= ~VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
54 tmp |= VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK |
55 VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK;
56 } else {
57 tmp |= VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
58 tmp &= ~(VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK |
59 VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK);
60 }
61
62 writel(tmp, &rpu_base->rpu_glbl_ctrl);
63}
64
Algapally Santosh Sagarb0142c12023-06-09 03:05:31 -0600[diff] [blame]65static void release_r5_reset(u8 mode)
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]66{
67 u32 tmp;
68
69 tmp = readl(&crlapb_base->rst_cpu_r5);
70 tmp &= ~(VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK |
71 VERSAL_CRLAPB_RST_LPD_R50_RST_MASK |
72 VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK);
73
74 if (mode == TCM_LOCK)
75 tmp &= ~VERSAL_CRLAPB_RST_LPD_R51_RST_MASK;
76
77 writel(tmp, &crlapb_base->rst_cpu_r5);
78}
79
Algapally Santosh Sagarb0142c12023-06-09 03:05:31 -0600[diff] [blame]80static void enable_clock_r5(void)
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]81{
82 u32 tmp;
83
84 tmp = readl(&crlapb_base->cpu_r5_ctrl);
85 tmp |= VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;
86 writel(tmp, &crlapb_base->cpu_r5_ctrl);
87}
88
89void initialize_tcm(bool mode)
90{
91 if (!mode) {
92 set_r5_tcm_mode(TCM_LOCK);
93 set_r5_halt_mode(HALT, TCM_LOCK);
94 enable_clock_r5();
95 release_r5_reset(TCM_LOCK);
96 } else {
97 set_r5_tcm_mode(TCM_SPLIT);
98 set_r5_halt_mode(HALT, TCM_SPLIT);
99 enable_clock_r5();
100 release_r5_reset(TCM_SPLIT);
101 }
102}
103
104void tcm_init(u8 mode)
105{
106 puts("WARNING: Initializing TCM overwrites TCM content\n");
107 initialize_tcm(mode);
108 memset((void *)VERSAL_TCM_BASE_ADDR, 0, VERSAL_TCM_SIZE);
109}