Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later OR MIT |
| 2 | /* |
| 3 | * Copyright 2023 Toradex |
| 4 | */ |
| 5 | |
| 6 | #include "k3-am625-verdin-wifi-dev-binman.dtsi" |
| 7 | |
| 8 | / { |
| 9 | aliases { |
| 10 | eeprom0 = &eeprom_module; |
| 11 | eeprom1 = &eeprom_carrier_board; |
| 12 | eeprom2 = &eeprom_display_adapter; |
| 13 | }; |
| 14 | |
| 15 | chosen { |
| 16 | tick-timer = &main_timer0; |
| 17 | }; |
| 18 | |
| 19 | memory@80000000 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 20 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 21 | }; |
| 22 | }; |
| 23 | |
| 24 | &cbass_main { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 25 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 26 | |
| 27 | timer@2400000 { |
| 28 | clock-frequency = <25000000>; |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 29 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 30 | }; |
| 31 | }; |
| 32 | |
| 33 | &cbass_mcu { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 34 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 35 | }; |
| 36 | |
| 37 | &cbass_wakeup { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 38 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 39 | }; |
| 40 | |
| 41 | &chipid { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 42 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 43 | }; |
| 44 | |
Roger Quadros | 74f5924 | 2023-10-28 20:36:02 +0300 | [diff] [blame] | 45 | &main_bcdma { |
| 46 | reg = <0x00 0x485c0100 0x00 0x100>, |
| 47 | <0x00 0x4c000000 0x00 0x20000>, |
| 48 | <0x00 0x4a820000 0x00 0x20000>, |
| 49 | <0x00 0x4aa40000 0x00 0x20000>, |
| 50 | <0x00 0x4bc00000 0x00 0x100000>, |
| 51 | <0x00 0x48600000 0x00 0x8000>, |
| 52 | <0x00 0x484a4000 0x00 0x2000>, |
| 53 | <0x00 0x484c2000 0x00 0x2000>; |
| 54 | reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", |
| 55 | "ringrt" , "cfg", "tchan", "rchan"; |
| 56 | }; |
| 57 | |
| 58 | &main_pktdma { |
| 59 | reg = <0x00 0x485c0000 0x00 0x100>, |
| 60 | <0x00 0x4a800000 0x00 0x20000>, |
| 61 | <0x00 0x4aa00000 0x00 0x20000>, |
| 62 | <0x00 0x4b800000 0x00 0x200000>, |
| 63 | <0x00 0x485e0000 0x00 0x10000>, |
| 64 | <0x00 0x484a0000 0x00 0x2000>, |
| 65 | <0x00 0x484c0000 0x00 0x2000>, |
| 66 | <0x00 0x48430000 0x00 0x1000>; |
| 67 | reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", |
| 68 | "cfg", "tchan", "rchan", "rflow"; |
| 69 | bootph-all; |
| 70 | }; |
| 71 | |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 72 | &cpsw3g { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 73 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 74 | }; |
| 75 | |
| 76 | &cpsw3g_phy0 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 77 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 78 | }; |
| 79 | |
| 80 | &cpsw3g_phy1 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 81 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 82 | }; |
| 83 | |
| 84 | &cpsw_port1 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 85 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 86 | }; |
| 87 | |
| 88 | &cpsw_port2 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 89 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 90 | }; |
| 91 | |
| 92 | /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ |
| 93 | &cpsw3g_mdio { |
| 94 | /delete-property/ assigned-clocks; |
| 95 | /delete-property/ assigned-clock-parents; |
| 96 | /delete-property/ assigned-clock-rates; |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 97 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 98 | }; |
| 99 | |
| 100 | &dmsc { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 101 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 102 | |
| 103 | k3_sysreset: sysreset-controller { |
| 104 | compatible = "ti,sci-sysreset"; |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 105 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 106 | }; |
| 107 | }; |
| 108 | |
| 109 | &dmss { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 110 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 111 | }; |
| 112 | |
| 113 | &fss { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 114 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 115 | }; |
| 116 | |
| 117 | &k3_clks { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 118 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 119 | }; |
| 120 | |
| 121 | &k3_pds { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 122 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 123 | }; |
| 124 | |
| 125 | &k3_reset { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 126 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 127 | }; |
| 128 | |
| 129 | &main_gpio0 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 130 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 131 | }; |
| 132 | |
| 133 | /* On-module I2C - PMIC_I2C */ |
| 134 | &main_i2c0 { |
| 135 | eeprom_module: eeprom@50 { |
| 136 | compatible = "i2c-eeprom"; |
| 137 | pagesize = <16>; |
| 138 | reg = <0x50>; |
| 139 | }; |
| 140 | }; |
| 141 | |
| 142 | /* Verdin I2C_1 */ |
| 143 | &main_i2c1 { |
| 144 | /* EEPROM on display adapter (MIPI DSI Display Adapter) */ |
| 145 | eeprom_display_adapter: eeprom@50 { |
| 146 | compatible = "i2c-eeprom"; |
| 147 | reg = <0x50>; |
| 148 | pagesize = <16>; |
| 149 | }; |
| 150 | |
| 151 | /* EEPROM on carrier board */ |
| 152 | eeprom_carrier_board: eeprom@57 { |
| 153 | compatible = "i2c-eeprom"; |
| 154 | reg = <0x57>; |
| 155 | pagesize = <16>; |
| 156 | }; |
| 157 | }; |
| 158 | |
| 159 | &main_pmx0 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 160 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 161 | }; |
| 162 | |
| 163 | /* Verdin UART_3, used as the Linux console */ |
| 164 | &main_uart0 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 165 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 166 | }; |
| 167 | |
| 168 | /* Verdin UART_1 */ |
| 169 | &main_uart1 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 170 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 171 | }; |
| 172 | |
| 173 | &mcu_pmx0 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 174 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 175 | }; |
| 176 | |
| 177 | &pinctrl_ctrl_sleep_moci { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 178 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 179 | }; |
| 180 | |
| 181 | &pinctrl_i2c0 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 182 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 183 | }; |
| 184 | |
| 185 | &pinctrl_i2c1 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 186 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 187 | }; |
| 188 | |
| 189 | &pinctrl_sdhci0 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 190 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 191 | }; |
| 192 | |
| 193 | &pinctrl_uart0 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 194 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 195 | }; |
| 196 | |
| 197 | &pinctrl_uart1 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 198 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 199 | }; |
| 200 | |
| 201 | &pinctrl_wkup_uart0 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 202 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 203 | }; |
| 204 | |
| 205 | &sdhci0 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 206 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 207 | }; |
| 208 | |
| 209 | &sdhci2 { |
| 210 | status = "disabled"; |
| 211 | }; |
| 212 | |
| 213 | &secure_proxy_main { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 214 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 215 | }; |
| 216 | |
| 217 | &verdin_ctrl_sleep_moci { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 218 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 219 | }; |
| 220 | |
| 221 | &wkup_conf { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 222 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 223 | }; |
| 224 | |
| 225 | /* Verdin UART_2 */ |
| 226 | &wkup_uart0 { |
Marcel Ziswiler | ddaf8ab | 2023-10-10 13:13:04 +0200 | [diff] [blame] | 227 | bootph-all; |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 228 | }; |