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git01.mediatek.com / filogic / uboot / b6f9cbb7e8e3c98d97bfb4d38b724c84d84d6ab1 / . / drivers / pinctrl / renesas / pfc-r8a77990.c
blob: f66b1597aa050520390c6fea4e9838eb4780fa21 [file] [log] [blame]
Tom Rini24672242018-06-01 21:10:18 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut68a77042018-04-26 13:09:20 +0200[diff] [blame]2/*
3 * R8A77990 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
Marek Vasut68a77042018-04-26 13:09:20 +0200[diff] [blame]12 */
13
14#include <common.h>
15#include <dm.h>
16#include <errno.h>
17#include <dm/pinctrl.h>
18#include <linux/kernel.h>
19
20#include "sh_pfc.h"
21
22#define CPU_ALL_PORT(fn, sfx) \
23 PORT_GP_18(0, fn, sfx), \
24 PORT_GP_23(1, fn, sfx), \
25 PORT_GP_26(2, fn, sfx), \
26 PORT_GP_16(3, fn, sfx), \
27 PORT_GP_11(4, fn, sfx), \
28 PORT_GP_20(5, fn, sfx), \
29 PORT_GP_18(6, fn, sfx)
30
31/*
32 * F_() : just information
33 * FM() : macro for FN_xxx / xxx_MARK
34 */
35
36/* GPSR0 */
37#define GPSR0_17 F_(SDA4, IP7_27_24)
38#define GPSR0_16 F_(SCL4, IP7_23_20)
39#define GPSR0_15 F_(D15, IP7_19_16)
40#define GPSR0_14 F_(D14, IP7_15_12)
41#define GPSR0_13 F_(D13, IP7_11_8)
42#define GPSR0_12 F_(D12, IP7_7_4)
43#define GPSR0_11 F_(D11, IP7_3_0)
44#define GPSR0_10 F_(D10, IP6_31_28)
45#define GPSR0_9 F_(D9, IP6_27_24)
46#define GPSR0_8 F_(D8, IP6_23_20)
47#define GPSR0_7 F_(D7, IP6_19_16)
48#define GPSR0_6 F_(D6, IP6_15_12)
49#define GPSR0_5 F_(D5, IP6_11_8)
50#define GPSR0_4 F_(D4, IP6_7_4)
51#define GPSR0_3 F_(D3, IP6_3_0)
52#define GPSR0_2 F_(D2, IP5_31_28)
53#define GPSR0_1 F_(D1, IP5_27_24)
54#define GPSR0_0 F_(D0, IP5_23_20)
55
56/* GPSR1 */
57#define GPSR1_22 F_(WE0_N, IP5_19_16)
58#define GPSR1_21 F_(CS0_N, IP5_15_12)
59#define GPSR1_20 FM(CLKOUT)
60#define GPSR1_19 F_(A19, IP5_11_8)
61#define GPSR1_18 F_(A18, IP5_7_4)
62#define GPSR1_17 F_(A17, IP5_3_0)
63#define GPSR1_16 F_(A16, IP4_31_28)
64#define GPSR1_15 F_(A15, IP4_27_24)
65#define GPSR1_14 F_(A14, IP4_23_20)
66#define GPSR1_13 F_(A13, IP4_19_16)
67#define GPSR1_12 F_(A12, IP4_15_12)
68#define GPSR1_11 F_(A11, IP4_11_8)
69#define GPSR1_10 F_(A10, IP4_7_4)
70#define GPSR1_9 F_(A9, IP4_3_0)
71#define GPSR1_8 F_(A8, IP3_31_28)
72#define GPSR1_7 F_(A7, IP3_27_24)
73#define GPSR1_6 F_(A6, IP3_23_20)
74#define GPSR1_5 F_(A5, IP3_19_16)
75#define GPSR1_4 F_(A4, IP3_15_12)
76#define GPSR1_3 F_(A3, IP3_11_8)
77#define GPSR1_2 F_(A2, IP3_7_4)
78#define GPSR1_1 F_(A1, IP3_3_0)
79#define GPSR1_0 F_(A0, IP2_31_28)
80
81/* GPSR2 */
82#define GPSR2_25 F_(EX_WAIT0, IP2_27_24)
83#define GPSR2_24 F_(RD_WR_N, IP2_23_20)
84#define GPSR2_23 F_(RD_N, IP2_19_16)
85#define GPSR2_22 F_(BS_N, IP2_15_12)
86#define GPSR2_21 FM(AVB_PHY_INT)
87#define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0)
88#define GPSR2_19 FM(AVB_RD3)
89#define GPSR2_18 F_(AVB_RD2, IP1_31_28)
90#define GPSR2_17 F_(AVB_RD1, IP1_27_24)
91#define GPSR2_16 F_(AVB_RD0, IP1_23_20)
92#define GPSR2_15 FM(AVB_RXC)
93#define GPSR2_14 FM(AVB_RX_CTL)
94#define GPSR2_13 F_(RPC_RESET_N, IP1_19_16)
95#define GPSR2_12 F_(RPC_INT_N, IP1_15_12)
96#define GPSR2_11 F_(QSPI1_SSL, IP1_11_8)
97#define GPSR2_10 F_(QSPI1_IO3, IP1_7_4)
98#define GPSR2_9 F_(QSPI1_IO2, IP1_3_0)
99#define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
100#define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24)
101#define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20)
102#define GPSR2_5 FM(QSPI0_SSL)
103#define GPSR2_4 F_(QSPI0_IO3, IP0_19_16)
104#define GPSR2_3 F_(QSPI0_IO2, IP0_15_12)
105#define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8)
106#define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4)
107#define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0)
108
109/* GPSR3 */
110#define GPSR3_15 F_(SD1_WP, IP11_7_4)
111#define GPSR3_14 F_(SD1_CD, IP11_3_0)
112#define GPSR3_13 F_(SD0_WP, IP10_31_28)
113#define GPSR3_12 F_(SD0_CD, IP10_27_24)
114#define GPSR3_11 F_(SD1_DAT3, IP9_11_8)
115#define GPSR3_10 F_(SD1_DAT2, IP9_7_4)
116#define GPSR3_9 F_(SD1_DAT1, IP9_3_0)
117#define GPSR3_8 F_(SD1_DAT0, IP8_31_28)
118#define GPSR3_7 F_(SD1_CMD, IP8_27_24)
119#define GPSR3_6 F_(SD1_CLK, IP8_23_20)
120#define GPSR3_5 F_(SD0_DAT3, IP8_19_16)
121#define GPSR3_4 F_(SD0_DAT2, IP8_15_12)
122#define GPSR3_3 F_(SD0_DAT1, IP8_11_8)
123#define GPSR3_2 F_(SD0_DAT0, IP8_7_4)
124#define GPSR3_1 F_(SD0_CMD, IP8_3_0)
125#define GPSR3_0 F_(SD0_CLK, IP7_31_28)
126
127/* GPSR4 */
128#define GPSR4_10 F_(SD3_DS, IP10_23_20)
129#define GPSR4_9 F_(SD3_DAT7, IP10_19_16)
130#define GPSR4_8 F_(SD3_DAT6, IP10_15_12)
131#define GPSR4_7 F_(SD3_DAT5, IP10_11_8)
132#define GPSR4_6 F_(SD3_DAT4, IP10_7_4)
133#define GPSR4_5 F_(SD3_DAT3, IP10_3_0)
134#define GPSR4_4 F_(SD3_DAT2, IP9_31_28)
135#define GPSR4_3 F_(SD3_DAT1, IP9_27_24)
136#define GPSR4_2 F_(SD3_DAT0, IP9_23_20)
137#define GPSR4_1 F_(SD3_CMD, IP9_19_16)
138#define GPSR4_0 F_(SD3_CLK, IP9_15_12)
139
140/* GPSR5 */
141#define GPSR5_19 F_(MLB_DAT, IP13_23_20)
142#define GPSR5_18 F_(MLB_SIG, IP13_19_16)
143#define GPSR5_17 F_(MLB_CLK, IP13_15_12)
144#define GPSR5_16 F_(SSI_SDATA9, IP13_11_8)
145#define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4)
146#define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0)
147#define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28)
148#define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24)
149#define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20)
150#define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16)
151#define GPSR5_9 F_(RX2_A, IP12_15_12)
152#define GPSR5_8 F_(TX2_A, IP12_11_8)
153#define GPSR5_7 F_(SCK2_A, IP12_7_4)
154#define GPSR5_6 F_(TX1, IP12_3_0)
155#define GPSR5_5 F_(RX1, IP11_31_28)
156#define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20)
157#define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
158#define GPSR5_2 F_(TX0_A, IP11_15_12)
159#define GPSR5_1 F_(RX0_A, IP11_11_8)
160#define GPSR5_0 F_(SCK0_A, IP11_27_24)
161
162/* GPSR6 */
163#define GPSR6_17 F_(USB30_PWEN, IP15_27_24)
164#define GPSR6_16 F_(SSI_SDATA6, IP15_19_16)
165#define GPSR6_15 F_(SSI_WS6, IP15_15_12)
166#define GPSR6_14 F_(SSI_SCK6, IP15_11_8)
167#define GPSR6_13 F_(SSI_SDATA5, IP15_7_4)
168#define GPSR6_12 F_(SSI_WS5, IP15_3_0)
169#define GPSR6_11 F_(SSI_SCK5, IP14_31_28)
170#define GPSR6_10 F_(SSI_SDATA4, IP14_27_24)
171#define GPSR6_9 F_(USB30_OVC, IP15_31_28)
172#define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20)
173#define GPSR6_7 F_(SSI_SDATA3, IP14_23_20)
174#define GPSR6_6 F_(SSI_WS349, IP14_19_16)
175#define GPSR6_5 F_(SSI_SCK349, IP14_15_12)
176#define GPSR6_4 F_(SSI_SDATA2, IP14_11_8)
177#define GPSR6_3 F_(SSI_SDATA1, IP14_7_4)
178#define GPSR6_2 F_(SSI_SDATA0, IP14_3_0)
179#define GPSR6_1 F_(SSI_WS01239, IP13_31_28)
180#define GPSR6_0 F_(SSI_SCK01239, IP13_27_24)
181
182/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
183#define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
184#define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
185#define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
186#define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
187#define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188#define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189#define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190#define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191#define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192#define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
193#define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
194#define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
195#define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
196#define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
197#define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
198#define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199#define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200#define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201#define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202#define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203#define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH_A) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205#define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206#define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209#define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215
216/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
217#define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249
250/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
251#define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB1_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283
284/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
285#define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317
318#define PINMUX_GPSR \
319\
320 \
321 \
322 \
323 \
324 \
325 \
326 GPSR2_25 \
327 GPSR2_24 \
328 GPSR2_23 \
329 GPSR1_22 GPSR2_22 \
330 GPSR1_21 GPSR2_21 \
331 GPSR1_20 GPSR2_20 \
332 GPSR1_19 GPSR2_19 GPSR5_19 \
333 GPSR1_18 GPSR2_18 GPSR5_18 \
334GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \
335GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \
336GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \
337GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \
338GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \
339GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \
340GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \
341GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
342GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
343GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
344GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
345GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
346GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
347GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
348GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
349GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
350GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
351GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
352
353#define PINMUX_IPSR \
354\
355FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
356FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
357FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
358FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
359FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
360FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
361FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
362FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
363\
364FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
365FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
366FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
367FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
368FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
369FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
370FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
371FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
372\
373FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
374FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
375FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
376FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
377FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
378FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
379FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
380FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
381\
382FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
383FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
384FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
385FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
386FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
387FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
388FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
389FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28
390
391/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
392#define MOD_SEL0_30_29 FM(SEL_ADGB_0) FM(SEL_ADGB_1) FM(SEL_ADGB_2) F_(0, 0)
393#define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1)
394#define MOD_SEL0_27_26 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) F_(0, 0)
395#define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1)
396#define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
397#define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
398#define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
399#define MOD_SEL0_21_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) FM(SEL_I2C1_2) FM(SEL_I2C1_3) FM(SEL_I2C1_4) F_(0, 0) F_(0, 0) F_(0, 0)
400#define MOD_SEL0_19_18_17 FM(SEL_I2C2_0) FM(SEL_I2C2_1) FM(SEL_I2C2_2) FM(SEL_I2C2_3) FM(SEL_I2C2_4) F_(0, 0) F_(0, 0) F_(0, 0)
401#define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
402#define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
403#define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
404#define MOD_SEL0_13_12 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) F_(0, 0)
405#define MOD_SEL0_11_10 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) F_(0, 0)
406#define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
407#define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
408#define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
409#define MOD_SEL0_6_5 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) FM(SEL_REMOCON_2) F_(0, 0)
410#define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
411#define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
412#define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
413#define MOD_SEL0_1_0 FM(SEL_SPEED_PULSE_IF_0) FM(SEL_SPEED_PULSE_IF_1) FM(SEL_SPEED_PULSE_IF_2) F_(0, 0)
414
415/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
416#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
417#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
418#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
419#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
420#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
421#define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
422#define MOD_SEL1_24_23_22 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) FM(SEL_HSCIF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
423#define MOD_SEL1_21_20_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) FM(SEL_HSCIF4_2) FM(SEL_HSCIF4_3) FM(SEL_HSCIF4_4) F_(0, 0) F_(0, 0) F_(0, 0)
424#define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1)
425#define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1)
426#define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
427#define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
428#define MOD_SEL1_14_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) FM(SEL_SCIF3_2) F_(0, 0)
429#define MOD_SEL1_12_11 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
430#define MOD_SEL1_10_9 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) FM(SEL_SCIF5_2) F_(0, 0)
431#define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
432#define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1)
433#define MOD_SEL1_6_5 FM(SEL_ADGC_0) FM(SEL_ADGC_1) FM(SEL_ADGC_2) F_(0, 0)
434#define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
435
436#define PINMUX_MOD_SELS \
437\
438 MOD_SEL1_31 \
439MOD_SEL0_30_29 MOD_SEL1_30 \
440 MOD_SEL1_29 \
441MOD_SEL0_28 MOD_SEL1_28 \
442MOD_SEL0_27_26 \
443 MOD_SEL1_26 \
444MOD_SEL0_25 MOD_SEL1_25 \
445MOD_SEL0_24 MOD_SEL1_24_23_22 \
446MOD_SEL0_23 \
447MOD_SEL0_22 \
448MOD_SEL0_21_20 MOD_SEL1_21_20_19 \
449MOD_SEL0_19_18_17 MOD_SEL1_18 \
450 MOD_SEL1_17 \
451MOD_SEL0_16 MOD_SEL1_16 \
452MOD_SEL0_15 MOD_SEL1_15 \
453MOD_SEL0_14 MOD_SEL1_14_13 \
454MOD_SEL0_13_12 \
455 MOD_SEL1_12_11 \
456MOD_SEL0_11_10 \
457 MOD_SEL1_10_9 \
458MOD_SEL0_9 \
459MOD_SEL0_8 MOD_SEL1_8 \
460MOD_SEL0_7 MOD_SEL1_7 \
461MOD_SEL0_6_5 MOD_SEL1_6_5 \
462MOD_SEL0_4 MOD_SEL1_4 \
463MOD_SEL0_3 \
464MOD_SEL0_2 \
465MOD_SEL0_1_0
466
467enum {
468 PINMUX_RESERVED = 0,
469
470 PINMUX_DATA_BEGIN,
471 GP_ALL(DATA),
472 PINMUX_DATA_END,
473
474#define F_(x, y)
475#define FM(x) FN_##x,
476 PINMUX_FUNCTION_BEGIN,
477 GP_ALL(FN),
478 PINMUX_GPSR
479 PINMUX_IPSR
480 PINMUX_MOD_SELS
481 PINMUX_FUNCTION_END,
482#undef F_
483#undef FM
484
485#define F_(x, y)
486#define FM(x) x##_MARK,
487 PINMUX_MARK_BEGIN,
488 PINMUX_GPSR
489 PINMUX_IPSR
490 PINMUX_MOD_SELS
491 PINMUX_MARK_END,
492#undef F_
493#undef FM
494};
495
496static const u16 pinmux_data[] = {
497 PINMUX_DATA_GP_ALL(),
498
499 /* IPSR0 */
500 PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK),
501 PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0),
502
503 PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0),
504 PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0),
505
506 PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1),
507 PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0),
508
509 PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2),
510 PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A),
511
512 PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3),
513 PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0),
514
515 PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK),
516 PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0),
517 PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1),
518 PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0),
519
520 PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0),
521 PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
522 PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B),
523 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0),
524
525 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
526 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
527 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
528 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
529
530 /* IPSR1 */
531 PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2),
532 PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0),
533 PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C),
534 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0),
535
536 PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3),
537 PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0),
538 PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2),
539 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0),
540
541 PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL),
542 PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0),
543 PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2),
544 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0),
545
546 PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N),
547 PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0),
548 PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2),
549 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0),
550
551 PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N),
552 PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0),
553 PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2),
554 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0),
555
556 PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0),
557
558 PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1),
559
560 PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2),
561
562 /* IPSR2 */
563 PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK),
564
565 PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO),
566
567 PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC),
568
569 PINMUX_IPSR_GPSR(IP2_15_12, BS_N),
570 PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0),
571 PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC),
572 PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK),
573 PINMUX_IPSR_GPSR(IP2_15_12, TX3_C),
574 PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1),
575
576 PINMUX_IPSR_GPSR(IP2_19_16, RD_N),
577 PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0),
578 PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK),
579 PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD),
580 PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2),
581 PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A),
582 PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1),
583
584 PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
585 PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
586 PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH_A),
587 PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
588 PINMUX_IPSR_GPSR(IP2_23_20, TX5_B),
589 PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2),
590 PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0),
591
592 PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0),
593 PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0),
594 PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE_A),
595 PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N),
596 PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1),
597 PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0),
598
599 PINMUX_IPSR_GPSR(IP2_31_28, A0),
600 PINMUX_IPSR_GPSR(IP2_31_28, IRQ0),
601 PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0),
602 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1),
603 PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0),
604 PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE),
605 PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3),
606 PINMUX_IPSR_GPSR(IP2_31_28, IERX),
607 PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE),
608
609 /* IPSR3 */
610 PINMUX_IPSR_GPSR(IP3_3_0, A1),
611 PINMUX_IPSR_GPSR(IP3_3_0, IRQ1),
612 PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0),
613 PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1),
614 PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0),
615 PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE),
616 PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1),
617 PINMUX_IPSR_GPSR(IP3_3_0, IETX),
618 PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE),
619
620 PINMUX_IPSR_GPSR(IP3_7_4, A2),
621 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
622 PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS),
623 PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB),
624 PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0),
625 PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP),
626 PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1),
627 PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE),
628
629 PINMUX_IPSR_GPSR(IP3_11_8, A3),
630 PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0),
631 PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0),
632 PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12),
633 PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0),
634 PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D),
635 PINMUX_IPSR_GPSR(IP3_11_8, IECLK),
636 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
637
638 PINMUX_IPSR_GPSR(IP3_15_12, A4),
639 PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0),
640 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
641 PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
642 PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
643 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
644 PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1),
645
646 PINMUX_IPSR_GPSR(IP3_19_16, A5),
647 PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0),
648 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1),
649 PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9),
650 PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1),
651 PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1),
652 PINMUX_IPSR_GPSR(IP3_19_16, QPOLA),
653
654 PINMUX_IPSR_GPSR(IP3_23_20, A6),
655 PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0),
656 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1),
657 PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10),
658 PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1),
659
660 PINMUX_IPSR_GPSR(IP3_27_24, A7),
661 PINMUX_IPSR_GPSR(IP3_27_24, TX4_A),
662 PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B),
663 PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11),
664 PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1),
665
666 PINMUX_IPSR_GPSR(IP3_31_28, A8),
667 PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0),
668 PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1),
669 PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2),
670 PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0),
671 PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC),
672 PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1),
673 PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS),
674
675 /* IPSR4 */
676 PINMUX_IPSR_GPSR(IP4_3_0, A9),
677 PINMUX_IPSR_GPSR(IP4_3_0, TX5_A),
678 PINMUX_IPSR_GPSR(IP4_3_0, IRQ3),
679 PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16),
680 PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0),
681 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7),
682 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15),
683
684 PINMUX_IPSR_GPSR(IP4_7_4, A10),
685 PINMUX_IPSR_GPSR(IP4_7_4, IRQ4),
686 PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1),
687 PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13),
688 PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0),
689 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5),
690 PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B),
691 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13),
692
693 PINMUX_IPSR_GPSR(IP4_11_8, A11),
694 PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0),
695 PINMUX_IPSR_GPSR(IP4_11_8, TX3_B),
696 PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C),
697 PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC),
698 PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1),
699 PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS),
700
701 PINMUX_IPSR_GPSR(IP4_15_12, A12),
702 PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0),
703 PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B),
704 PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17),
705 PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0),
706 PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6),
707 PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14),
708
709 PINMUX_IPSR_GPSR(IP4_19_16, A13),
710 PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0),
711 PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1),
712 PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14),
713 PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3),
714 PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2),
715 PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2),
716
717 PINMUX_IPSR_GPSR(IP4_23_20, A14),
718 PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1),
719 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1),
720 PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15),
721 PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D),
722 PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3),
723 PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3),
724
725 PINMUX_IPSR_GPSR(IP4_27_24, A15),
726 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2),
727 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B),
728 PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18),
729 PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0),
730 PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4),
731 PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4),
732
733 PINMUX_IPSR_GPSR(IP4_31_28, A16),
734 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC),
735 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B),
736 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19),
737 PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0),
738 PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5),
739 PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5),
740
741 /* IPSR5 */
742 PINMUX_IPSR_GPSR(IP5_3_0, A17),
743 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
744 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20),
745 PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0),
746 PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6),
747 PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6),
748
749 PINMUX_IPSR_GPSR(IP5_7_4, A18),
750 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
751 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21),
752 PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0),
753 PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0),
754 PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4),
755 PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0),
756
757 PINMUX_IPSR_GPSR(IP5_11_8, A19),
758 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
759 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22),
760 PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0),
761 PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1),
762 PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E),
763 PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1),
764
765 PINMUX_IPSR_GPSR(IP5_15_12, CS0_N),
766 PINMUX_IPSR_GPSR(IP5_15_12, SCL5),
767 PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0),
768 PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1),
769 PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16),
770
771 PINMUX_IPSR_GPSR(IP5_19_16, WE0_N),
772 PINMUX_IPSR_GPSR(IP5_19_16, SDA5),
773 PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1),
774 PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1),
775 PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17),
776
777 PINMUX_IPSR_GPSR(IP5_23_20, D0),
778 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
779 PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2),
780 PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2),
781 PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18),
782
783 PINMUX_IPSR_GPSR(IP5_27_24, D1),
784 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0),
785 PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0),
786 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
787 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
788 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
789 PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
790 PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
791
792 PINMUX_IPSR_GPSR(IP5_31_28, D2),
793 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0),
794 PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2),
795 PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0),
796 PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3),
797 PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2),
798 PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19),
799
800 /* IPSR6 */
801 PINMUX_IPSR_GPSR(IP6_3_0, D3),
802 PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A),
803 PINMUX_IPSR_GPSR(IP6_3_0, TX5_C),
804 PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0),
805 PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4),
806 PINMUX_IPSR_GPSR(IP6_3_0, TX4_C),
807 PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20),
808
809 PINMUX_IPSR_GPSR(IP6_7_4, D4),
810 PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
811 PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
812 PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
813 PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0),
814 PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
815 PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
816
817 PINMUX_IPSR_GPSR(IP6_11_8, D5),
818 PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0),
819 PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1),
820 PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5),
821 PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1),
822 PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21),
823
824 PINMUX_IPSR_GPSR(IP6_15_12, D6),
825 PINMUX_IPSR_GPSR(IP6_15_12, TX3_A),
826 PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B),
827 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6),
828 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1),
829 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22),
830
831 PINMUX_IPSR_GPSR(IP6_19_16, D7),
832 PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX),
833 PINMUX_IPSR_GPSR(IP6_19_16, IRQ5),
834 PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX),
835 PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0),
836 PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1),
837
838 PINMUX_IPSR_GPSR(IP6_23_20, D8),
839 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0),
840 PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1),
841 PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0),
842 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7),
843 PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1),
844 PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4),
845 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23),
846
847 PINMUX_IPSR_GPSR(IP6_27_24, D9),
848 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0),
849 PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0),
850 PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0),
851 PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1),
852 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4),
853 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8),
854
855 PINMUX_IPSR_GPSR(IP6_31_28, D10),
856 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0),
857 PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0),
858 PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1),
859 PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1),
860 PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E),
861 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9),
862
863 /* IPSR7 */
864 PINMUX_IPSR_GPSR(IP7_3_0, D11),
865 PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A),
866 PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0),
867 PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2),
868 PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1),
869 PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4),
870 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10),
871
872 PINMUX_IPSR_GPSR(IP7_7_4, D12),
873 PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX),
874 PINMUX_IPSR_GPSR(IP7_7_4, TX4_B),
875 PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX),
876 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0),
877 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1),
878
879 PINMUX_IPSR_GPSR(IP7_11_8, D13),
880 PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX),
881 PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1),
882 PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX),
883 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0),
884 PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1),
885 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1),
886
887 PINMUX_IPSR_GPSR(IP7_15_12, D14),
888 PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK),
889 PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0),
890 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A),
891 PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1),
892 PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1),
893
894 PINMUX_IPSR_GPSR(IP7_19_16, D15),
895 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A),
896 PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A),
897 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A),
898 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3),
899 PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11),
900
901 PINMUX_IPSR_GPSR(IP7_23_20, SCL4),
902 PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26),
903 PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0),
904 PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1),
905 PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1),
906 PINMUX_IPSR_GPSR(IP7_23_20, QCLK),
907
908 PINMUX_IPSR_GPSR(IP7_27_24, SDA4),
909 PINMUX_IPSR_GPSR(IP7_27_24, WE1_N),
910 PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1),
911 PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1),
912 PINMUX_IPSR_GPSR(IP7_27_24, QPOLB),
913
914 PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK),
915 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8),
916 PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2),
917 PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1),
918 PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4),
919 PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1),
920
921 /* IPSR8 */
922 PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD),
923 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9),
924 PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1),
925 PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1),
926
927 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0),
928 PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10),
929 PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B),
930 PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1),
931
932 PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1),
933 PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11),
934 PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2),
935 PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1),
936 PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1),
937
938 PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2),
939 PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12),
940 PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2),
941 PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1),
942 PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B),
943
944 PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3),
945 PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13),
946 PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2),
947 PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4),
948 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2),
949 PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
950
951 PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
952 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
953
954 PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
955 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
956
957 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
958 PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1),
959
960 /* IPSR9 */
961 PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
962 PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1),
963
964 PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
965 PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1),
966
967 PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
968 PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1),
969
970 PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
971 PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
972
973 PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD),
974 PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N),
975
976 PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0),
977 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0),
978
979 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1),
980 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1),
981
982 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2),
983 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2),
984
985 /* IPSR10 */
986 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3),
987 PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3),
988
989 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4),
990 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4),
991
992 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5),
993 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5),
994
995 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6),
996 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6),
997
998 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7),
999 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7),
1000
1001 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS),
1002 PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
1003
1004 PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
1005 PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A),
1006 PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
1007 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1008 PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
1009 PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
1010 PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
1011 PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
1012
1013 PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
1014 PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A),
1015 PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
1016 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1017 PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
1018 PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
1019 PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
1020 PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
1021
1022 /* IPSR11 */
1023 PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
1024 PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0),
1025 PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
1026 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1027 PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
1028
1029 PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
1030 PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0),
1031 PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
1032 PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
1033 PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
1034
1035 PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
1036 PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
1037 PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
1038 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
1039 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
1040
1041 PINMUX_IPSR_GPSR(IP11_15_12, TX0_A),
1042 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
1043 PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
1044 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
1045 PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
1046
1047 PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
1048 PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0),
1049 PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
1050 PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
1051 PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
1052 PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
1053
1054 PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0),
1055 PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0),
1056 PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
1057 PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
1058 PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
1059 PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0),
1060
1061 PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
1062 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
1063 PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
1064 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
1065 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1066 PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
1067 PINMUX_IPSR_GPSR(IP11_27_24, USB1_ID),
1068
1069 PINMUX_IPSR_GPSR(IP11_31_28, RX1),
1070 PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1),
1071 PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1),
1072 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B),
1073
1074 /* IPSR12 */
1075 PINMUX_IPSR_GPSR(IP12_3_0, TX1),
1076 PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B),
1077 PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1),
1078 PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B),
1079
1080 PINMUX_IPSR_GPSR(IP12_7_4, SCK2_A),
1081 PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0),
1082 PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0),
1083 PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N),
1084 PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0),
1085 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0),
1086 PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1),
1087
1088 PINMUX_IPSR_GPSR(IP12_11_8, TX2_A),
1089 PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0),
1090 PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A),
1091 PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0),
1092 PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0),
1093 PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1),
1094
1095 PINMUX_IPSR_GPSR(IP12_15_12, RX2_A),
1096 PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A),
1097 PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A),
1098 PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0),
1099 PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0),
1100 PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1),
1101
1102 PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK),
1103 PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78),
1104
1105 PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD),
1106 PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78),
1107 PINMUX_IPSR_GPSR(IP12_23_20, TX2_B),
1108
1109 PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD),
1110 PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7),
1111 PINMUX_IPSR_GPSR(IP12_27_24, RX2_B),
1112
1113 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1114 PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B),
1115 PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8),
1116
1117 /* IPSR13 */
1118 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1119 PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0),
1120 PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4),
1121 PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0),
1122 PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C),
1123 PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0),
1124
1125 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1126 PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A),
1127 PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4),
1128 PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0),
1129 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2),
1130 PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A),
1131
1132 PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9),
1133 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0),
1134 PINMUX_IPSR_GPSR(IP13_11_8, SCK1),
1135
1136 PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK),
1137 PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1),
1138 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0),
1139 PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1),
1140 PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1),
1141 PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A),
1142
1143 PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG),
1144 PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1),
1145 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
1146 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
1147 PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
1148 PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
1149
1150 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
1151 PINMUX_IPSR_GPSR(IP13_23_20, TX0_B),
1152 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0),
1153 PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A),
1154
1155 PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239),
1156
1157 PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239),
1158
1159 /* IPSR14 */
1160 PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0),
1161
1162 PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1),
1163 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1),
1164 PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1),
1165
1166 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2),
1167 PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B),
1168 PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0),
1169 PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1),
1170
1171 PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349),
1172 PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2),
1173
1174 PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349),
1175 PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2),
1176
1177 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3),
1178 PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C),
1179 PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1),
1180 PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1),
1181
1182 PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4),
1183 PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0),
1184 PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1),
1185
1186 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5),
1187 PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1),
1188 PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B),
1189 PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3),
1190 PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1),
1191
1192 /* IPSR15 */
1193 PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5),
1194 PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B),
1195 PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1),
1196 PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3),
1197
1198 PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5),
1199 PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1),
1200 PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2),
1201 PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0),
1202
1203 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6),
1204 PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0),
1205 PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2),
1206 PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1),
1207 PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1),
1208 PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B),
1209
1210 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6),
1211 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1212 PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C),
1213 PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
1214 PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
1215 PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
1216 PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
1217
1218 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
1219 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1220 PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C),
1221 PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3),
1222 PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3),
1223 PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1),
1224 PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B),
1225
1226 PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA),
1227
1228 PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN),
1229 PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A),
1230
1231 PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC),
1232 PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0),
1233};
1234
1235static const struct sh_pfc_pin pinmux_pins[] = {
1236 PINMUX_GPIO_GP_ALL(),
1237};
1238
1239static const struct sh_pfc_pin_group pinmux_groups[] = {
1240};
1241
1242static const struct sh_pfc_function pinmux_functions[] = {
1243};
1244
1245static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1246#define F_(x, y) FN_##y
1247#define FM(x) FN_##x
1248 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
1249 0, 0,
1250 0, 0,
1251 0, 0,
1252 0, 0,
1253 0, 0,
1254 0, 0,
1255 0, 0,
1256 0, 0,
1257 0, 0,
1258 0, 0,
1259 0, 0,
1260 0, 0,
1261 0, 0,
1262 0, 0,
1263 GP_0_17_FN, GPSR0_17,
1264 GP_0_16_FN, GPSR0_16,
1265 GP_0_15_FN, GPSR0_15,
1266 GP_0_14_FN, GPSR0_14,
1267 GP_0_13_FN, GPSR0_13,
1268 GP_0_12_FN, GPSR0_12,
1269 GP_0_11_FN, GPSR0_11,
1270 GP_0_10_FN, GPSR0_10,
1271 GP_0_9_FN, GPSR0_9,
1272 GP_0_8_FN, GPSR0_8,
1273 GP_0_7_FN, GPSR0_7,
1274 GP_0_6_FN, GPSR0_6,
1275 GP_0_5_FN, GPSR0_5,
1276 GP_0_4_FN, GPSR0_4,
1277 GP_0_3_FN, GPSR0_3,
1278 GP_0_2_FN, GPSR0_2,
1279 GP_0_1_FN, GPSR0_1,
1280 GP_0_0_FN, GPSR0_0, }
1281 },
1282 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
1283 0, 0,
1284 0, 0,
1285 0, 0,
1286 0, 0,
1287 0, 0,
1288 0, 0,
1289 0, 0,
1290 0, 0,
1291 0, 0,
1292 GP_1_22_FN, GPSR1_22,
1293 GP_1_21_FN, GPSR1_21,
1294 GP_1_20_FN, GPSR1_20,
1295 GP_1_19_FN, GPSR1_19,
1296 GP_1_18_FN, GPSR1_18,
1297 GP_1_17_FN, GPSR1_17,
1298 GP_1_16_FN, GPSR1_16,
1299 GP_1_15_FN, GPSR1_15,
1300 GP_1_14_FN, GPSR1_14,
1301 GP_1_13_FN, GPSR1_13,
1302 GP_1_12_FN, GPSR1_12,
1303 GP_1_11_FN, GPSR1_11,
1304 GP_1_10_FN, GPSR1_10,
1305 GP_1_9_FN, GPSR1_9,
1306 GP_1_8_FN, GPSR1_8,
1307 GP_1_7_FN, GPSR1_7,
1308 GP_1_6_FN, GPSR1_6,
1309 GP_1_5_FN, GPSR1_5,
1310 GP_1_4_FN, GPSR1_4,
1311 GP_1_3_FN, GPSR1_3,
1312 GP_1_2_FN, GPSR1_2,
1313 GP_1_1_FN, GPSR1_1,
1314 GP_1_0_FN, GPSR1_0, }
1315 },
1316 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
1317 0, 0,
1318 0, 0,
1319 0, 0,
1320 0, 0,
1321 0, 0,
1322 0, 0,
1323 GP_2_25_FN, GPSR2_25,
1324 GP_2_24_FN, GPSR2_24,
1325 GP_2_23_FN, GPSR2_23,
1326 GP_2_22_FN, GPSR2_22,
1327 GP_2_21_FN, GPSR2_21,
1328 GP_2_20_FN, GPSR2_20,
1329 GP_2_19_FN, GPSR2_19,
1330 GP_2_18_FN, GPSR2_18,
1331 GP_2_17_FN, GPSR2_17,
1332 GP_2_16_FN, GPSR2_16,
1333 GP_2_15_FN, GPSR2_15,
1334 GP_2_14_FN, GPSR2_14,
1335 GP_2_13_FN, GPSR2_13,
1336 GP_2_12_FN, GPSR2_12,
1337 GP_2_11_FN, GPSR2_11,
1338 GP_2_10_FN, GPSR2_10,
1339 GP_2_9_FN, GPSR2_9,
1340 GP_2_8_FN, GPSR2_8,
1341 GP_2_7_FN, GPSR2_7,
1342 GP_2_6_FN, GPSR2_6,
1343 GP_2_5_FN, GPSR2_5,
1344 GP_2_4_FN, GPSR2_4,
1345 GP_2_3_FN, GPSR2_3,
1346 GP_2_2_FN, GPSR2_2,
1347 GP_2_1_FN, GPSR2_1,
1348 GP_2_0_FN, GPSR2_0, }
1349 },
1350 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
1351 0, 0,
1352 0, 0,
1353 0, 0,
1354 0, 0,
1355 0, 0,
1356 0, 0,
1357 0, 0,
1358 0, 0,
1359 0, 0,
1360 0, 0,
1361 0, 0,
1362 0, 0,
1363 0, 0,
1364 0, 0,
1365 0, 0,
1366 0, 0,
1367 GP_3_15_FN, GPSR3_15,
1368 GP_3_14_FN, GPSR3_14,
1369 GP_3_13_FN, GPSR3_13,
1370 GP_3_12_FN, GPSR3_12,
1371 GP_3_11_FN, GPSR3_11,
1372 GP_3_10_FN, GPSR3_10,
1373 GP_3_9_FN, GPSR3_9,
1374 GP_3_8_FN, GPSR3_8,
1375 GP_3_7_FN, GPSR3_7,
1376 GP_3_6_FN, GPSR3_6,
1377 GP_3_5_FN, GPSR3_5,
1378 GP_3_4_FN, GPSR3_4,
1379 GP_3_3_FN, GPSR3_3,
1380 GP_3_2_FN, GPSR3_2,
1381 GP_3_1_FN, GPSR3_1,
1382 GP_3_0_FN, GPSR3_0, }
1383 },
1384 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
1385 0, 0,
1386 0, 0,
1387 0, 0,
1388 0, 0,
1389 0, 0,
1390 0, 0,
1391 0, 0,
1392 0, 0,
1393 0, 0,
1394 0, 0,
1395 0, 0,
1396 0, 0,
1397 0, 0,
1398 0, 0,
1399 0, 0,
1400 0, 0,
1401 0, 0,
1402 0, 0,
1403 0, 0,
1404 0, 0,
1405 0, 0,
1406 GP_4_10_FN, GPSR4_10,
1407 GP_4_9_FN, GPSR4_9,
1408 GP_4_8_FN, GPSR4_8,
1409 GP_4_7_FN, GPSR4_7,
1410 GP_4_6_FN, GPSR4_6,
1411 GP_4_5_FN, GPSR4_5,
1412 GP_4_4_FN, GPSR4_4,
1413 GP_4_3_FN, GPSR4_3,
1414 GP_4_2_FN, GPSR4_2,
1415 GP_4_1_FN, GPSR4_1,
1416 GP_4_0_FN, GPSR4_0, }
1417 },
1418 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
1419 0, 0,
1420 0, 0,
1421 0, 0,
1422 0, 0,
1423 0, 0,
1424 0, 0,
1425 0, 0,
1426 0, 0,
1427 0, 0,
1428 0, 0,
1429 0, 0,
1430 0, 0,
1431 GP_5_19_FN, GPSR5_19,
1432 GP_5_18_FN, GPSR5_18,
1433 GP_5_17_FN, GPSR5_17,
1434 GP_5_16_FN, GPSR5_16,
1435 GP_5_15_FN, GPSR5_15,
1436 GP_5_14_FN, GPSR5_14,
1437 GP_5_13_FN, GPSR5_13,
1438 GP_5_12_FN, GPSR5_12,
1439 GP_5_11_FN, GPSR5_11,
1440 GP_5_10_FN, GPSR5_10,
1441 GP_5_9_FN, GPSR5_9,
1442 GP_5_8_FN, GPSR5_8,
1443 GP_5_7_FN, GPSR5_7,
1444 GP_5_6_FN, GPSR5_6,
1445 GP_5_5_FN, GPSR5_5,
1446 GP_5_4_FN, GPSR5_4,
1447 GP_5_3_FN, GPSR5_3,
1448 GP_5_2_FN, GPSR5_2,
1449 GP_5_1_FN, GPSR5_1,
1450 GP_5_0_FN, GPSR5_0, }
1451 },
1452 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
1453 0, 0,
1454 0, 0,
1455 0, 0,
1456 0, 0,
1457 0, 0,
1458 0, 0,
1459 0, 0,
1460 0, 0,
1461 0, 0,
1462 0, 0,
1463 0, 0,
1464 0, 0,
1465 0, 0,
1466 0, 0,
1467 GP_6_17_FN, GPSR6_17,
1468 GP_6_16_FN, GPSR6_16,
1469 GP_6_15_FN, GPSR6_15,
1470 GP_6_14_FN, GPSR6_14,
1471 GP_6_13_FN, GPSR6_13,
1472 GP_6_12_FN, GPSR6_12,
1473 GP_6_11_FN, GPSR6_11,
1474 GP_6_10_FN, GPSR6_10,
1475 GP_6_9_FN, GPSR6_9,
1476 GP_6_8_FN, GPSR6_8,
1477 GP_6_7_FN, GPSR6_7,
1478 GP_6_6_FN, GPSR6_6,
1479 GP_6_5_FN, GPSR6_5,
1480 GP_6_4_FN, GPSR6_4,
1481 GP_6_3_FN, GPSR6_3,
1482 GP_6_2_FN, GPSR6_2,
1483 GP_6_1_FN, GPSR6_1,
1484 GP_6_0_FN, GPSR6_0, }
1485 },
1486#undef F_
1487#undef FM
1488
1489#define F_(x, y) x,
1490#define FM(x) FN_##x,
1491 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
1492 IP0_31_28
1493 IP0_27_24
1494 IP0_23_20
1495 IP0_19_16
1496 IP0_15_12
1497 IP0_11_8
1498 IP0_7_4
1499 IP0_3_0 }
1500 },
1501 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
1502 IP1_31_28
1503 IP1_27_24
1504 IP1_23_20
1505 IP1_19_16
1506 IP1_15_12
1507 IP1_11_8
1508 IP1_7_4
1509 IP1_3_0 }
1510 },
1511 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
1512 IP2_31_28
1513 IP2_27_24
1514 IP2_23_20
1515 IP2_19_16
1516 IP2_15_12
1517 IP2_11_8
1518 IP2_7_4
1519 IP2_3_0 }
1520 },
1521 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
1522 IP3_31_28
1523 IP3_27_24
1524 IP3_23_20
1525 IP3_19_16
1526 IP3_15_12
1527 IP3_11_8
1528 IP3_7_4
1529 IP3_3_0 }
1530 },
1531 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
1532 IP4_31_28
1533 IP4_27_24
1534 IP4_23_20
1535 IP4_19_16
1536 IP4_15_12
1537 IP4_11_8
1538 IP4_7_4
1539 IP4_3_0 }
1540 },
1541 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
1542 IP5_31_28
1543 IP5_27_24
1544 IP5_23_20
1545 IP5_19_16
1546 IP5_15_12
1547 IP5_11_8
1548 IP5_7_4
1549 IP5_3_0 }
1550 },
1551 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
1552 IP6_31_28
1553 IP6_27_24
1554 IP6_23_20
1555 IP6_19_16
1556 IP6_15_12
1557 IP6_11_8
1558 IP6_7_4
1559 IP6_3_0 }
1560 },
1561 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
1562 IP7_31_28
1563 IP7_27_24
1564 IP7_23_20
1565 IP7_19_16
1566 IP7_15_12
1567 IP7_11_8
1568 IP7_7_4
1569 IP7_3_0 }
1570 },
1571 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
1572 IP8_31_28
1573 IP8_27_24
1574 IP8_23_20
1575 IP8_19_16
1576 IP8_15_12
1577 IP8_11_8
1578 IP8_7_4
1579 IP8_3_0 }
1580 },
1581 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
1582 IP9_31_28
1583 IP9_27_24
1584 IP9_23_20
1585 IP9_19_16
1586 IP9_15_12
1587 IP9_11_8
1588 IP9_7_4
1589 IP9_3_0 }
1590 },
1591 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
1592 IP10_31_28
1593 IP10_27_24
1594 IP10_23_20
1595 IP10_19_16
1596 IP10_15_12
1597 IP10_11_8
1598 IP10_7_4
1599 IP10_3_0 }
1600 },
1601 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
1602 IP11_31_28
1603 IP11_27_24
1604 IP11_23_20
1605 IP11_19_16
1606 IP11_15_12
1607 IP11_11_8
1608 IP11_7_4
1609 IP11_3_0 }
1610 },
1611 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
1612 IP12_31_28
1613 IP12_27_24
1614 IP12_23_20
1615 IP12_19_16
1616 IP12_15_12
1617 IP12_11_8
1618 IP12_7_4
1619 IP12_3_0 }
1620 },
1621 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
1622 IP13_31_28
1623 IP13_27_24
1624 IP13_23_20
1625 IP13_19_16
1626 IP13_15_12
1627 IP13_11_8
1628 IP13_7_4
1629 IP13_3_0 }
1630 },
1631 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
1632 IP14_31_28
1633 IP14_27_24
1634 IP14_23_20
1635 IP14_19_16
1636 IP14_15_12
1637 IP14_11_8
1638 IP14_7_4
1639 IP14_3_0 }
1640 },
1641 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
1642 IP15_31_28
1643 IP15_27_24
1644 IP15_23_20
1645 IP15_19_16
1646 IP15_15_12
1647 IP15_11_8
1648 IP15_7_4
1649 IP15_3_0 }
1650 },
1651#undef F_
1652#undef FM
1653
1654#define F_(x, y) x,
1655#define FM(x) FN_##x,
1656 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
1657 1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1,
1658 1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) {
1659 /* RESERVED 31 */
1660 0, 0,
1661 MOD_SEL0_30_29
1662 MOD_SEL0_28
1663 MOD_SEL0_27_26
1664 MOD_SEL0_25
1665 MOD_SEL0_24
1666 MOD_SEL0_23
1667 MOD_SEL0_22
1668 MOD_SEL0_21_20
1669 MOD_SEL0_19_18_17
1670 MOD_SEL0_16
1671 MOD_SEL0_15
1672 MOD_SEL0_14
1673 MOD_SEL0_13_12
1674 MOD_SEL0_11_10
1675 MOD_SEL0_9
1676 MOD_SEL0_8
1677 MOD_SEL0_7
1678 MOD_SEL0_6_5
1679 MOD_SEL0_4
1680 MOD_SEL0_3
1681 MOD_SEL0_2
1682 MOD_SEL0_1_0 }
1683 },
1684 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
1685 1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
1686 1, 2, 2, 2, 1, 1, 2, 1, 4) {
1687 MOD_SEL1_31
1688 MOD_SEL1_30
1689 MOD_SEL1_29
1690 MOD_SEL1_28
1691 /* RESERVED 27 */
1692 0, 0,
1693 MOD_SEL1_26
1694 MOD_SEL1_25
1695 MOD_SEL1_24_23_22
1696 MOD_SEL1_21_20_19
1697 MOD_SEL1_18
1698 MOD_SEL1_17
1699 MOD_SEL1_16
1700 MOD_SEL1_15
1701 MOD_SEL1_14_13
1702 MOD_SEL1_12_11
1703 MOD_SEL1_10_9
1704 MOD_SEL1_8
1705 MOD_SEL1_7
1706 MOD_SEL1_6_5
1707 MOD_SEL1_4
1708 /* RESERVED 3, 2, 1, 0 */
1709 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1710 },
1711 { },
1712};
1713
1714const struct sh_pfc_soc_info r8a77990_pinmux_info = {
1715 .name = "r8a77990_pfc",
1716 .unlock_reg = 0xe6060000, /* PMMR */
1717
1718 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1719
1720 .pins = pinmux_pins,
1721 .nr_pins = ARRAY_SIZE(pinmux_pins),
1722 .groups = pinmux_groups,
1723 .nr_groups = ARRAY_SIZE(pinmux_groups),
1724 .functions = pinmux_functions,
1725 .nr_functions = ARRAY_SIZE(pinmux_functions),
1726
1727 .cfg_regs = pinmux_config_regs,
1728
1729 .pinmux_data = pinmux_data,
1730 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
1731};