| Peng Fan | adbbc75 | 2021-08-07 16:01:04 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2020 NXP |
| 4 | */ |
| 5 | |
| 6 | #ifndef __MACH_IMX8ULP_IOMUX_H__ |
| 7 | #define __MACH_IMX8ULP_IOMUX_H__ |
| 8 | |
| 9 | typedef u64 iomux_cfg_t; |
| 10 | |
| 11 | #define MUX_CTRL_OFS_SHIFT 0 |
| 12 | #define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT) |
| 13 | #define MUX_SEL_INPUT_OFS_SHIFT 16 |
| 14 | #define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0xffff << MUX_SEL_INPUT_OFS_SHIFT) |
| 15 | |
| 16 | #define MUX_MODE_SHIFT 32 |
| 17 | #define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT) |
| 18 | #define MUX_SEL_INPUT_SHIFT 38 |
| 19 | #define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) |
| 20 | #define MUX_PAD_CTRL_SHIFT 42 |
| 21 | #define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT) |
| 22 | |
| 23 | #define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) |
| 24 | |
| 25 | #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, sel_input, pad_ctrl) \ |
| 26 | (((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ |
| 27 | ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ |
| 28 | ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ |
| 29 | ((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \ |
| 30 | ((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) |
| 31 | |
| 32 | #define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad)) |
| 33 | |
| 34 | #define IOMUX_CONFIG_MPORTS 0x20 |
| 35 | #define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \ MUX_MODE_SHIFT) |
| 36 | |
| 37 | /* Bit definition below needs to be fixed acccording to ulp rm */ |
| 38 | |
| 39 | #define NO_PAD_CTRL BIT(18) |
| 40 | #define PAD_CTL_OBE_ENABLE BIT(17) |
| 41 | #define PAD_CTL_IBE_ENABLE BIT(16) |
| 42 | #define PAD_CTL_DSE BIT(6) |
| 43 | #define PAD_CTL_ODE BIT(5) |
| 44 | #define PAD_CTL_SRE_FAST (0 << 2) |
| 45 | #define PAD_CTL_SRE_SLOW BIT(2) |
| 46 | #define PAD_CTL_PUE BIT(1) |
| 47 | #define PAD_CTL_PUS_UP (BIT(0) | PAD_CTL_PUE) |
| 48 | #define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE) |
| 49 | |
| 50 | #define IOMUXC_PCR_MUX_ALT0 (0 << 8) |
| 51 | #define IOMUXC_PCR_MUX_ALT1 (1 << 8) |
| 52 | #define IOMUXC_PCR_MUX_ALT2 (2 << 8) |
| 53 | #define IOMUXC_PCR_MUX_ALT3 (3 << 8) |
| 54 | #define IOMUXC_PCR_MUX_ALT4 (4 << 8) |
| 55 | #define IOMUXC_PCR_MUX_ALT5 (5 << 8) |
| 56 | #define IOMUXC_PCR_MUX_ALT6 (6 << 8) |
| 57 | #define IOMUXC_PCR_MUX_ALT7 (7 << 8) |
| 58 | #define IOMUXC_PCR_MUX_ALT8 (8 << 8) |
| 59 | #define IOMUXC_PCR_MUX_ALT9 (9 << 8) |
| 60 | #define IOMUXC_PCR_MUX_ALT10 (10 << 8) |
| 61 | #define IOMUXC_PCR_MUX_ALT11 (11 << 8) |
| 62 | #define IOMUXC_PCR_MUX_ALT12 (12 << 8) |
| 63 | #define IOMUXC_PCR_MUX_ALT13 (13 << 8) |
| 64 | #define IOMUXC_PCR_MUX_ALT14 (14 << 8) |
| 65 | #define IOMUXC_PCR_MUX_ALT15 (15 << 8) |
| 66 | |
| 67 | #define IOMUXC_PSMI_IMUX_ALT0 (0x0) |
| 68 | #define IOMUXC_PSMI_IMUX_ALT1 (0x1) |
| 69 | #define IOMUXC_PSMI_IMUX_ALT2 (0x2) |
| 70 | #define IOMUXC_PSMI_IMUX_ALT3 (0x3) |
| 71 | #define IOMUXC_PSMI_IMUX_ALT4 (0x4) |
| 72 | #define IOMUXC_PSMI_IMUX_ALT5 (0x5) |
| 73 | #define IOMUXC_PSMI_IMUX_ALT6 (0x6) |
| 74 | #define IOMUXC_PSMI_IMUX_ALT7 (0x7) |
| 75 | |
| 76 | #define IOMUXC_PCR_MUX_ALT_SHIFT (8) |
| 77 | #define IOMUXC_PCR_MUX_ALT_MASK (0xF00) |
| 78 | #define IOMUXC_PSMI_IMUX_ALT_SHIFT (0) |
| 79 | |
| 80 | void imx8ulp_iomux_setup_pad(iomux_cfg_t pad); |
| 81 | void imx8ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, unsigned int count); |
| 82 | #endif |