blob: cfb7ceacc1dac6232c91b6fe189f412da70b4f2f [file] [log] [blame]
Wolfgang Denk9da240c2005-10-05 00:19:34 +02001/*
2 * Rick Bronson <rick@efn.org>
3 *
4 * Configuation settings for the AT91RM9200DK board.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * Adatped for KwikByte KB920x board from at91rm9200dk.h: 22APR2005
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
Jens Scharsig128ecd02010-02-03 22:45:42 +010032#define CONFIG_AT91_LEGACY
33
Wolfgang Denk9da240c2005-10-05 00:19:34 +020034/* ARM asynchronous clock */
35#define AT91C_MAIN_CLOCK 180000000 /* from 10 MHz crystal */
36#define AT91C_MASTER_CLOCK 60000000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
37
38#define AT91_SLOW_CLOCK 32768 /* slow clock */
39
40#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
41#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
42/* Only define one of the following, based on board type */
43/* #define CONFIG_KB9200 1 KwikByte KB9202 board */
44/* #define CONFIG_KB9201 1 KwikByte KB9202 board */
45#define CONFIG_KB9202 1 /* KwikByte KB9202 board */
46
47#define CONFIG_KB920x 1 /* Any KB920x board */
48#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
49#define USE_920T_MMU 1
50
51#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
52#define CONFIG_SETUP_MEMORY_TAGS 1
53#define CONFIG_INITRD_TAG 1
54
55#define CONFIG_SKIP_LOWLEVEL_INIT
56
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020057#define CONFIG_SYS_LONGHELP
Wolfgang Denk9da240c2005-10-05 00:19:34 +020058
Wolfgang Denk311f8892008-05-04 21:34:23 +020059#ifndef roundup
60#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
61#endif
Wolfgang Denk9da240c2005-10-05 00:19:34 +020062/*
63 * Size of malloc() pool
64 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065#define CONFIG_SYS_MALLOC_LEN (roundup(CONFIG_ENV_SIZE,4096) + 128*1024)
Wolfgang Denk9da240c2005-10-05 00:19:34 +020066
67#define CONFIG_BAUDRATE 115200
68
69/*
70 * Hardware drivers
71 */
72
73/* define one of these to choose the DBGU, USART0 or USART1 as console */
Jean-Christophe PLAGNIOL-VILLARDd7b468c2009-03-27 23:26:43 +010074#define CONFIG_AT91RM9200_USART
Wolfgang Denk9da240c2005-10-05 00:19:34 +020075#define CONFIG_DBGU
76#undef CONFIG_USART0
77#undef CONFIG_USART1
78
79#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
80
81#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
82
83#define CONFIG_BOOTDELAY 3
84#define CONFIG_ENV_OVERWRITE 1
85
Jon Loeligerca8b5662007-07-04 22:32:51 -050086
87/*
Jon Loeliger140b69c2007-07-10 09:38:02 -050088 * BOOTP options
89 */
90#define CONFIG_BOOTP_BOOTFILESIZE
91#define CONFIG_BOOTP_BOOTPATH
92#define CONFIG_BOOTP_GATEWAY
93#define CONFIG_BOOTP_HOSTNAME
94
95
96/*
Jon Loeligerca8b5662007-07-04 22:32:51 -050097 * Command line configuration.
98 */
99#include <config_cmd_default.h>
100
101#define CONFIG_CMD_I2C
102#define CONFIG_CMD_PING
103#define CONFIG_CMD_DHCP
104
105#undef CONFIG_CMD_BDI
106#undef CONFIG_CMD_FPGA
107#undef CONFIG_CMD_MISC
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200108
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200109
110#define CONFIG_NR_DRAM_BANKS 1
111#define PHYS_SDRAM 0x20000000
112#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
113
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200114#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
115#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - (512*1024)
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200116
Jens Scharsigdab7cb82010-01-23 12:03:45 +0100117#define CONFIG_NET_MULTI 1
118#ifdef CONFIG_NET_MULTI
119#define CONFIG_DRIVER_AT91EMAC 1
120#define CONFIG_SYS_RX_ETH_BUFFER 8
121#else
122#define CONFIG_DRIVER_ETHER 1
123#endif
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200124#define CONFIG_NET_RETRY_COUNT 20
125
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126#define CONFIG_SYS_FLASH_BASE 0x10000000
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200127
128#ifdef CONFIG_KB9202
129#define PHYS_FLASH_SIZE 0x1000000
130#else
131#define PHYS_FLASH_SIZE 0x200000
132#endif
133
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#define CONFIG_SYS_MAX_FLASH_BANKS 1
135#define CONFIG_SYS_MAX_FLASH_SECT 256
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200136
137#define CONFIG_HARD_I2C
138
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200139#define CONFIG_ENV_IS_IN_EEPROM
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200140
141#ifdef CONFIG_KB9202
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200142#define CONFIG_ENV_OFFSET 0x3E00
143#define CONFIG_ENV_SIZE 0x0200
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200144#else
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200145#define CONFIG_ENV_OFFSET 0x1000
146#define CONFIG_ENV_SIZE 0x1000
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200147#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
149#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
150#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
151#define CONFIG_SYS_I2C_SPEED 50000
152#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
153#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200154
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200156
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200157#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200158
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200159#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
160#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
161#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
162#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200163
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200164#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165#define CONFIG_SYS_FLASH_CFI
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200166
167#ifndef __ASSEMBLY__
168/*-----------------------------------------------------------------------
169 * Board specific extension for bd_info
170 *
171 * This structure is embedded in the global bd_info (bd_t) structure
172 * and can be used by the board specific code (eg board/...)
173 */
174
175struct bd_info_ext {
176 /* helper variable for board environment handling
177 *
178 * env_crc_valid == 0 => uninitialised
179 * env_crc_valid > 0 => environment crc in flash is valid
180 * env_crc_valid < 0 => environment crc in flash is invalid
181 */
182 int env_crc_valid;
183};
184#endif
185
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200186#define CONFIG_SYS_HZ 1000
187#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
Wolfgang Denk9da240c2005-10-05 00:19:34 +0200188 /* AT91C_TC_TIMER_DIV1_CLOCK */
189
190#define CONFIG_STACKSIZE (32*1024) /* regular stack */
191
192#ifdef CONFIG_USE_IRQ
193#error CONFIG_USE_IRQ not supported
194#endif
195
196#endif