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git01.mediatek.com / filogic / uboot / b67d3adcb3ad07e374cb224173ec8a29a4378a2c / . / arch / arm / dts / fsl-ls1028a-qds.dts
blob: 029a8e386b1d93c8f590dde0e4cadd5793fe16b2 [file] [log] [blame]
Yuantian Tang473bbc42019-04-10 16:43:35 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP ls1028AQDS device tree source
4 *
5 * Copyright 2019 NXP
6 *
7 */
8
9/dts-v1/;
10
11#include "fsl-ls1028a.dtsi"
12
13/ {
14 model = "NXP Layerscape 1028a QDS Board";
15 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
Kuldeep Singhbaab2462019-11-06 16:38:00 +0530[diff] [blame]16 aliases {
17 spi0 = &fspi;
18 };
19
Yuantian Tang473bbc42019-04-10 16:43:35 +0800[diff] [blame]20};
21
22&dspi0 {
23 status = "okay";
24};
25
26&dspi1 {
27 status = "okay";
28};
29
30&dspi2 {
31 status = "okay";
32};
33
34&esdhc0 {
35 status = "okay";
36};
37
38&esdhc1 {
39 status = "okay";
Alex Marginean679cd542019-08-07 19:30:03 +0300[diff] [blame]40
Kuldeep Singhbaab2462019-11-06 16:38:00 +0530[diff] [blame]41};
42
43&fspi {
44 status = "okay";
45
46 mt35xu02g0: flash@0 {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "jedec,spi-nor";
50 spi-max-frequency = <50000000>;
51 reg = <0>;
Kuldeep Singhf1b22292020-03-14 18:23:55 +0530[diff] [blame]52 spi-rx-bus-width = <8>;
53 spi-tx-bus-width = <1>;
Kuldeep Singhbaab2462019-11-06 16:38:00 +0530[diff] [blame]54 };
Yuantian Tang473bbc42019-04-10 16:43:35 +0800[diff] [blame]55};
56
57&i2c0 {
58 status = "okay";
Chuanhua Hanc6c006a2019-07-10 15:48:39 +0800[diff] [blame]59 u-boot,dm-pre-reloc;
60
Alex Marginean679cd542019-08-07 19:30:03 +0300[diff] [blame]61 fpga@66 {
62 #address-cells = <1>;
63 #size-cells = <0>;
64 compatible = "simple-mfd";
65 reg = <0x66>;
66
67 mux-mdio@54 {
68 #address-cells = <1>;
69 #size-cells = <0>;
70 compatible = "mdio-mux-i2creg";
71 reg = <0x54>;
72 #mux-control-cells = <1>;
73 mux-reg-masks = <0x54 0xf0>;
74 mdio-parent-bus = <&mdio0>;
75
76 /* on-board MDIO with a single RGMII PHY */
77 mdio@00 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 reg = <0x00>;
81
82 qds_phy0: phy@5 {
83 reg = <5>;
84 };
85 };
86 /* slot 1 */
87 slot1: mdio@40 {
88 #address-cells = <1>;
89 #size-cells = <0>;
90 reg = <0x40>;
91 };
92 /* slot 2 */
93 slot2: mdio@50 {
94 #address-cells = <1>;
95 #size-cells = <0>;
96 reg = <0x50>;
97 };
98 /* slot 3 */
99 slot3: mdio@60 {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 reg = <0x60>;
103 };
104 /* slot 4 */
105 slot4: mdio@70 {
106 #address-cells = <1>;
107 #size-cells = <0>;
108 reg = <0x70>;
109 };
110 };
111 };
112
Chuanhua Hanc6c006a2019-07-10 15:48:39 +0800[diff] [blame]113 i2c-mux@77 {
114 compatible = "nxp,pca9547";
115 reg = <0x77>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 };
Yuantian Tang473bbc42019-04-10 16:43:35 +0800[diff] [blame]119};
120
121&i2c1 {
122 status = "okay";
Chuanhua Han7657bc32019-07-10 15:48:40 +0800[diff] [blame]123
124 rtc@51 {
125 compatible = "pcf2127-rtc";
126 reg = <0x51>;
127 };
Yuantian Tang473bbc42019-04-10 16:43:35 +0800[diff] [blame]128};
129
130&i2c2 {
131 status = "okay";
132};
133
134&i2c3 {
135 status = "okay";
136};
137
138&i2c4 {
139 status = "okay";
140};
141
142&i2c5 {
143 status = "okay";
144};
145
146&i2c6 {
147 status = "okay";
148};
149
150&i2c7 {
151 status = "okay";
152};
153
154&sata {
155 status = "okay";
156};
157
158&serial0 {
159 status = "okay";
160};
161
162&serial1 {
163 status = "okay";
164};
165
166&usb1 {
167 status = "okay";
168};
169
170&usb2 {
171 status = "okay";
172};
Alex Marginean3be715e2019-07-03 12:11:43 +0300[diff] [blame]173
174&enetc1 {
175 status = "okay";
176 phy-mode = "rgmii";
177 phy-handle = <&qds_phy0>;
178};
179
180&mdio0 {
181 status = "okay";
Alex Marginean3be715e2019-07-03 12:11:43 +0300[diff] [blame]182};