Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Daniel Gorsulowski | 6f196d5 | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2007-2008 |
Stelian Pop | 5ee0c7f | 2011-11-01 00:00:39 +0100 | [diff] [blame] | 4 | * Stelian Pop <stelian@popies.net> |
Daniel Gorsulowski | 6f196d5 | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 5 | * Lead Tech Design <www.leadtechdesign.com> |
| 6 | * |
Daniel Gorsulowski | 2acb23b | 2015-11-02 07:59:49 +0100 | [diff] [blame] | 7 | * (C) Copyright 2009-2015 |
Daniel Gorsulowski | 6f196d5 | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 8 | * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> |
| 9 | * esd electronic system design gmbh <www.esd.eu> |
| 10 | * |
| 11 | * Configuation settings for the esd MEESC board. |
Daniel Gorsulowski | 6f196d5 | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | #ifndef __CONFIG_H |
| 15 | #define __CONFIG_H |
| 16 | |
Matthias Fuchs | 2d56c2b | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 17 | /* |
| 18 | * SoC must be defined first, before hardware.h is included. |
| 19 | * In this case SoC is defined in boards.cfg. |
| 20 | */ |
| 21 | #include <asm/hardware.h> |
| 22 | |
| 23 | /* |
Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 24 | * Warning: changing CONFIG_TEXT_BASE requires |
Matthias Fuchs | 2d56c2b | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 25 | * adapting the initial boot program. |
| 26 | * Since the linker has to swallow that define, we must use a pure |
| 27 | * hex number here! |
| 28 | */ |
Matthias Fuchs | 2d56c2b | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 29 | |
| 30 | /* ARM asynchronous clock */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 31 | #define CFG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ |
| 32 | #define CFG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ |
Daniel Gorsulowski | 6f196d5 | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 33 | |
Matthias Fuchs | 2d56c2b | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 34 | /* Misc CPU related */ |
Daniel Gorsulowski | 6f196d5 | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 35 | |
Daniel Gorsulowski | 6f196d5 | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 36 | /* |
| 37 | * Hardware drivers |
| 38 | */ |
| 39 | |
Daniel Gorsulowski | 6f196d5 | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 40 | /* |
Matthias Fuchs | 2d56c2b | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 41 | * SDRAM: 1 bank, min 32, max 128 MB |
| 42 | * Initialized before u-boot gets started. |
| 43 | */ |
Daniel Gorsulowski | 2acb23b | 2015-11-02 07:59:49 +0100 | [diff] [blame] | 44 | #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ |
| 45 | #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ |
| 46 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 47 | #define CFG_SYS_SDRAM_BASE PHYS_SDRAM |
| 48 | #define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE |
Matthias Fuchs | 2d56c2b | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 49 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 50 | #define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 |
| 51 | #define CFG_SYS_INIT_RAM_SIZE (16 * 1024) |
Daniel Gorsulowski | 6f196d5 | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 52 | |
Daniel Gorsulowski | 6f196d5 | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 53 | /* NAND flash */ |
| 54 | #ifdef CONFIG_CMD_NAND |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 55 | # define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ |
| 56 | # define CFG_SYS_NAND_MASK_ALE (1 << 21) |
| 57 | # define CFG_SYS_NAND_MASK_CLE (1 << 22) |
| 58 | # define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) |
| 59 | # define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) |
Daniel Gorsulowski | 6f196d5 | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 60 | #endif |
| 61 | |
Daniel Gorsulowski | 54b531a | 2009-09-29 08:03:12 +0200 | [diff] [blame] | 62 | /* hw-controller addresses */ |
Tom Rini | 67a4cfe | 2022-12-04 10:03:48 -0500 | [diff] [blame] | 63 | #define CFG_ET1100_BASE 0x70000000 |
Matthias Fuchs | 2d56c2b | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 64 | |
Daniel Gorsulowski | 6f196d5 | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 65 | #endif |