blob: 38da55c70bfe7df500f87c56f3e780e9129dbf2d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +02002/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +02005 * Lead Tech Design <www.leadtechdesign.com>
6 *
Daniel Gorsulowski2acb23b2015-11-02 07:59:49 +01007 * (C) Copyright 2009-2015
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +02008 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
9 * esd electronic system design gmbh <www.esd.eu>
10 *
11 * Configuation settings for the esd MEESC board.
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +020012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +000017/*
18 * SoC must be defined first, before hardware.h is included.
19 * In this case SoC is defined in boards.cfg.
20 */
21#include <asm/hardware.h>
22
23/*
Simon Glass72cc5382022-10-20 18:22:39 -060024 * Warning: changing CONFIG_TEXT_BASE requires
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +000025 * adapting the initial boot program.
26 * Since the linker has to swallow that define, we must use a pure
27 * hex number here!
28 */
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +000029
30/* ARM asynchronous clock */
Tom Rini6a5dccc2022-11-16 13:10:41 -050031#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
32#define CFG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +020033
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +000034/* Misc CPU related */
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +020035
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +020036/*
37 * Hardware drivers
38 */
39
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +020040/*
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +000041 * SDRAM: 1 bank, min 32, max 128 MB
42 * Initialized before u-boot gets started.
43 */
Daniel Gorsulowski2acb23b2015-11-02 07:59:49 +010044#define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */
45#define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */
46
Tom Rinibb4dd962022-11-16 13:10:37 -050047#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
48#define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +000049
Tom Rini6a5dccc2022-11-16 13:10:41 -050050#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0
51#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +020052
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +020053/* NAND flash */
54#ifdef CONFIG_CMD_NAND
Tom Rinib4213492022-11-12 17:36:51 -050055# define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
56# define CFG_SYS_NAND_MASK_ALE (1 << 21)
57# define CFG_SYS_NAND_MASK_CLE (1 << 22)
58# define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
59# define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +020060#endif
61
Daniel Gorsulowski54b531a2009-09-29 08:03:12 +020062/* hw-controller addresses */
Tom Rini67a4cfe2022-12-04 10:03:48 -050063#define CFG_ET1100_BASE 0x70000000
Matthias Fuchs2d56c2b2011-07-19 01:56:06 +000064
Daniel Gorsulowski6f196d52009-06-30 21:03:37 +020065#endif