| Masahiro Yamada | 77f0822 | 2015-02-27 02:27:02 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011-2015 Panasonic Corporation |
| 3 | * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <mach/sbc-regs.h> |
| 11 | #include <mach/sg-regs.h> |
| 12 | |
| 13 | void sbc_init(void) |
| 14 | { |
| 15 | u32 tmp; |
| 16 | |
| 17 | /* system bus output enable */ |
| 18 | tmp = readl(PC0CTRL); |
| 19 | tmp &= 0xfffffcff; |
| 20 | writel(tmp, PC0CTRL); |
| 21 | |
| 22 | /* |
| 23 | * SBCTRL0* does not need settings because PH1-sLD8 has no support for |
| 24 | * XECS0. The boot swap must be enabled to boot from the support card. |
| 25 | */ |
| 26 | |
| 27 | if (boot_is_swapped()) { |
| 28 | /* XECS1 : boot memory if boot swap is on */ |
| 29 | writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); |
| 30 | writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); |
| 31 | writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); |
| 32 | writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); |
| 33 | } |
| 34 | |
| 35 | /* XECS4 : sub memory */ |
| 36 | writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40); |
| 37 | writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41); |
| 38 | writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42); |
| 39 | writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44); |
| 40 | |
| 41 | /* XECS5 : peripherals */ |
| 42 | writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50); |
| 43 | writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51); |
| 44 | writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52); |
| 45 | writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54); |
| 46 | |
| 47 | /* base address regsiters */ |
| 48 | writel(0x0000bc01, SBBASE0); /* boot memory */ |
| 49 | writel(0x0900bfff, SBBASE1); /* dummy */ |
| 50 | writel(0x0400bc01, SBBASE4); /* sub memory */ |
| 51 | writel(0x0800bf01, SBBASE5); /* peripherals */ |
| 52 | |
| 53 | sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */ |
| 54 | sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */ |
| 55 | |
| 56 | /* dummy read to assure write process */ |
| 57 | readl(SG_PINCTRL(0)); |
| 58 | } |