Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2013 |
| 4 | * David Feng <fenghua@phytium.com.cn> |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_ARMV8_MMU_H_ |
| 8 | #define _ASM_ARMV8_MMU_H_ |
| 9 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 10 | /* |
Sergey Temerkhanov | 78eaa49 | 2015-10-14 09:55:45 -0700 | [diff] [blame] | 11 | * block/section address mask and size definitions. |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 12 | */ |
Alexander Graf | e317fe8 | 2016-03-04 01:09:47 +0100 | [diff] [blame] | 13 | |
| 14 | /* PAGE_SHIFT determines the page size */ |
| 15 | #undef PAGE_SIZE |
Alexander Graf | e317fe8 | 2016-03-04 01:09:47 +0100 | [diff] [blame] | 16 | #define PAGE_SHIFT 12 |
| 17 | #define PAGE_SIZE (1 << PAGE_SHIFT) |
Andy Yan | d2eb8c1 | 2017-08-17 15:55:50 +0800 | [diff] [blame] | 18 | #define PAGE_MASK (~(PAGE_SIZE - 1)) |
Alexander Graf | e317fe8 | 2016-03-04 01:09:47 +0100 | [diff] [blame] | 19 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 20 | /***************************************************************/ |
| 21 | |
| 22 | /* |
| 23 | * Memory types |
| 24 | */ |
| 25 | #define MT_DEVICE_NGNRNE 0 |
| 26 | #define MT_DEVICE_NGNRE 1 |
| 27 | #define MT_DEVICE_GRE 2 |
| 28 | #define MT_NORMAL_NC 3 |
| 29 | #define MT_NORMAL 4 |
| 30 | |
Sergey Temerkhanov | 78eaa49 | 2015-10-14 09:55:45 -0700 | [diff] [blame] | 31 | #define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \ |
| 32 | (0x04 << (MT_DEVICE_NGNRE * 8)) | \ |
| 33 | (0x0c << (MT_DEVICE_GRE * 8)) | \ |
| 34 | (0x44 << (MT_NORMAL_NC * 8)) | \ |
| 35 | (UL(0xff) << (MT_NORMAL * 8))) |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 36 | |
| 37 | /* |
| 38 | * Hardware page table definitions. |
| 39 | * |
Sergey Temerkhanov | 78eaa49 | 2015-10-14 09:55:45 -0700 | [diff] [blame] | 40 | */ |
| 41 | |
Alexander Graf | e317fe8 | 2016-03-04 01:09:47 +0100 | [diff] [blame] | 42 | #define PTE_TYPE_MASK (3 << 0) |
| 43 | #define PTE_TYPE_FAULT (0 << 0) |
| 44 | #define PTE_TYPE_TABLE (3 << 0) |
Peng Fan | e0e9871 | 2017-11-28 10:31:28 +0800 | [diff] [blame] | 45 | #define PTE_TYPE_PAGE (3 << 0) |
Alexander Graf | e317fe8 | 2016-03-04 01:09:47 +0100 | [diff] [blame] | 46 | #define PTE_TYPE_BLOCK (1 << 0) |
York Sun | 5bb14e0 | 2017-03-06 09:02:33 -0800 | [diff] [blame] | 47 | #define PTE_TYPE_VALID (1 << 0) |
Sergey Temerkhanov | 78eaa49 | 2015-10-14 09:55:45 -0700 | [diff] [blame] | 48 | |
Alexander Graf | e317fe8 | 2016-03-04 01:09:47 +0100 | [diff] [blame] | 49 | #define PTE_TABLE_PXN (1UL << 59) |
| 50 | #define PTE_TABLE_XN (1UL << 60) |
| 51 | #define PTE_TABLE_AP (1UL << 61) |
| 52 | #define PTE_TABLE_NS (1UL << 63) |
Sergey Temerkhanov | 78eaa49 | 2015-10-14 09:55:45 -0700 | [diff] [blame] | 53 | |
| 54 | /* |
| 55 | * Block |
| 56 | */ |
Alexander Graf | e317fe8 | 2016-03-04 01:09:47 +0100 | [diff] [blame] | 57 | #define PTE_BLOCK_MEMTYPE(x) ((x) << 2) |
Alexander Graf | ce0a64e | 2016-03-04 01:09:54 +0100 | [diff] [blame] | 58 | #define PTE_BLOCK_NS (1 << 5) |
Alexander Graf | e317fe8 | 2016-03-04 01:09:47 +0100 | [diff] [blame] | 59 | #define PTE_BLOCK_NON_SHARE (0 << 8) |
| 60 | #define PTE_BLOCK_OUTER_SHARE (2 << 8) |
| 61 | #define PTE_BLOCK_INNER_SHARE (3 << 8) |
| 62 | #define PTE_BLOCK_AF (1 << 10) |
| 63 | #define PTE_BLOCK_NG (1 << 11) |
| 64 | #define PTE_BLOCK_PXN (UL(1) << 53) |
| 65 | #define PTE_BLOCK_UXN (UL(1) << 54) |
Sergey Temerkhanov | 78eaa49 | 2015-10-14 09:55:45 -0700 | [diff] [blame] | 66 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 67 | /* |
| 68 | * AttrIndx[2:0] |
| 69 | */ |
| 70 | #define PMD_ATTRINDX(t) ((t) << 2) |
| 71 | #define PMD_ATTRINDX_MASK (7 << 2) |
York Sun | 5bb14e0 | 2017-03-06 09:02:33 -0800 | [diff] [blame] | 72 | #define PMD_ATTRMASK (PTE_BLOCK_PXN | \ |
| 73 | PTE_BLOCK_UXN | \ |
| 74 | PMD_ATTRINDX_MASK | \ |
| 75 | PTE_TYPE_VALID) |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * TCR flags. |
| 79 | */ |
| 80 | #define TCR_T0SZ(x) ((64 - (x)) << 0) |
| 81 | #define TCR_IRGN_NC (0 << 8) |
| 82 | #define TCR_IRGN_WBWA (1 << 8) |
| 83 | #define TCR_IRGN_WT (2 << 8) |
| 84 | #define TCR_IRGN_WBNWA (3 << 8) |
| 85 | #define TCR_IRGN_MASK (3 << 8) |
| 86 | #define TCR_ORGN_NC (0 << 10) |
| 87 | #define TCR_ORGN_WBWA (1 << 10) |
| 88 | #define TCR_ORGN_WT (2 << 10) |
| 89 | #define TCR_ORGN_WBNWA (3 << 10) |
| 90 | #define TCR_ORGN_MASK (3 << 10) |
| 91 | #define TCR_SHARED_NON (0 << 12) |
Zhichun Hua | 5d849ac | 2015-06-29 15:49:37 +0800 | [diff] [blame] | 92 | #define TCR_SHARED_OUTER (2 << 12) |
| 93 | #define TCR_SHARED_INNER (3 << 12) |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 94 | #define TCR_TG0_4K (0 << 14) |
| 95 | #define TCR_TG0_64K (1 << 14) |
| 96 | #define TCR_TG0_16K (2 << 14) |
Alexander Graf | f03c0e4 | 2016-03-04 01:09:46 +0100 | [diff] [blame] | 97 | #define TCR_EPD1_DISABLE (1 << 23) |
Sergey Temerkhanov | 78eaa49 | 2015-10-14 09:55:45 -0700 | [diff] [blame] | 98 | |
Thierry Reding | a3e45ab | 2015-08-20 11:52:14 +0200 | [diff] [blame] | 99 | #define TCR_EL1_RSVD (1 << 31) |
| 100 | #define TCR_EL2_RSVD (1 << 31 | 1 << 23) |
| 101 | #define TCR_EL3_RSVD (1 << 31 | 1 << 23) |
| 102 | |
York Sun | ef63194 | 2014-06-23 15:15:53 -0700 | [diff] [blame] | 103 | #ifndef __ASSEMBLY__ |
York Sun | ef63194 | 2014-06-23 15:15:53 -0700 | [diff] [blame] | 104 | static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) |
| 105 | { |
| 106 | asm volatile("dsb sy"); |
| 107 | if (el == 1) { |
| 108 | asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory"); |
| 109 | asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); |
| 110 | asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory"); |
| 111 | } else if (el == 2) { |
| 112 | asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory"); |
| 113 | asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); |
| 114 | asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory"); |
| 115 | } else if (el == 3) { |
| 116 | asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory"); |
| 117 | asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); |
| 118 | asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory"); |
| 119 | } else { |
| 120 | hang(); |
| 121 | } |
| 122 | asm volatile("isb"); |
| 123 | } |
Sergey Temerkhanov | 78eaa49 | 2015-10-14 09:55:45 -0700 | [diff] [blame] | 124 | |
| 125 | struct mm_region { |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 126 | u64 virt; |
| 127 | u64 phys; |
Sergey Temerkhanov | 78eaa49 | 2015-10-14 09:55:45 -0700 | [diff] [blame] | 128 | u64 size; |
| 129 | u64 attrs; |
| 130 | }; |
Alexander Graf | 6b3e7ca | 2016-03-04 01:09:48 +0100 | [diff] [blame] | 131 | |
| 132 | extern struct mm_region *mem_map; |
York Sun | a81fcd1 | 2016-06-24 16:46:20 -0700 | [diff] [blame] | 133 | void setup_pgtables(void); |
| 134 | u64 get_tcr(int el, u64 *pips, u64 *pva_bits); |
York Sun | ef63194 | 2014-06-23 15:15:53 -0700 | [diff] [blame] | 135 | #endif |
Sergey Temerkhanov | 78eaa49 | 2015-10-14 09:55:45 -0700 | [diff] [blame] | 136 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 137 | #endif /* _ASM_ARMV8_MMU_H_ */ |