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wdenk359733b2003-03-31 17:27:09 +00001/*
2 * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
wdenk359733b2003-03-31 17:27:09 +00005 */
6
7/*
8 * File: cpu_init.c
wdenk57b2d802003-06-27 21:31:46 +00009 *
wdenk359733b2003-03-31 17:27:09 +000010 * Discription: Contains initialisation functions to setup
Wolfgang Denka1be4762008-05-20 16:00:29 +020011 * the cpu properly
wdenk359733b2003-03-31 17:27:09 +000012 *
13 */
14
15#include <common.h>
16#include <mpc5xx.h>
17#include <watchdog.h>
18
19/*
wdenk57b2d802003-06-27 21:31:46 +000020 * Setup essential cpu registers to run
wdenk359733b2003-03-31 17:27:09 +000021 */
22void cpu_init_f (volatile immap_t * immr)
23{
24 volatile memctl5xx_t *memctl = &immr->im_memctl;
25 ulong reg;
26
27 /* SYPCR - contains watchdog control. This will enable watchdog */
28 /* if CONFIG_WATCHDOG is set */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020029 immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
wdenk359733b2003-03-31 17:27:09 +000030
31#if defined(CONFIG_WATCHDOG)
32 reset_5xx_watchdog (immr);
wdenk57b2d802003-06-27 21:31:46 +000033#endif
wdenk359733b2003-03-31 17:27:09 +000034
35 /* SIUMCR - contains debug pin configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020036 immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
wdenk359733b2003-03-31 17:27:09 +000037
38 /* Initialize timebase. Unlock TBSCRK */
39 immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020040 immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
wdenk359733b2003-03-31 17:27:09 +000041
42 /* Full IMB bus speed */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020043 immr->im_uimb.uimb_umcr = CONFIG_SYS_UMCR;
wdenk57b2d802003-06-27 21:31:46 +000044
wdenk359733b2003-03-31 17:27:09 +000045 /* Time base and decrementer will be enables (TBE) */
Simon Glass4c974d72017-03-28 10:27:24 -060046 /* in timer_init() in time.c called from board_init_f(). */
wdenk57b2d802003-06-27 21:31:46 +000047
wdenk359733b2003-03-31 17:27:09 +000048 /* Initialize the PIT. Unlock PISCRK */
49 immr->im_sitk.sitk_piscrk = KAPWR_KEY;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020050 immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
wdenk359733b2003-03-31 17:27:09 +000051
wdenkbc01dd52004-01-02 16:05:07 +000052#if !defined(CONFIG_PATI)
53 /* PATI sest PLL in start.S */
wdenk359733b2003-03-31 17:27:09 +000054 /* PLL (CPU clock) settings */
55 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
56
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020057 /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
58 * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
59 * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the currentMF
wdenk359733b2003-03-31 17:27:09 +000060 * field value.
61 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020062#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0)
63 reg = CONFIG_SYS_PLPRCR; /* reset control bits */
wdenk359733b2003-03-31 17:27:09 +000064#else
65 reg = immr->im_clkrst.car_plprcr;
66 reg &= PLPRCR_MF_MSK; /* isolate MF field */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067 reg |= CONFIG_SYS_PLPRCR; /* reset control bits */
wdenk359733b2003-03-31 17:27:09 +000068#endif
69 immr->im_clkrst.car_plprcr = reg;
70
wdenkbc01dd52004-01-02 16:05:07 +000071#endif /* !defined(CONFIG_PATI) */
72
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073 /* System integration timers. CONFIG_SYS_MASK has EBDF configuration */
wdenk359733b2003-03-31 17:27:09 +000074 immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
75 reg = immr->im_clkrst.car_sccr;
76 reg &= SCCR_MASK;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020077 reg |= CONFIG_SYS_SCCR;
wdenk359733b2003-03-31 17:27:09 +000078 immr->im_clkrst.car_sccr = reg;
79
80 /* Memory Controller */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081 memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
82 memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
wdenk359733b2003-03-31 17:27:09 +000083
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
85 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
86 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
wdenk359733b2003-03-31 17:27:09 +000087#endif
88
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
90 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
91 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
wdenk359733b2003-03-31 17:27:09 +000092#endif
93
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
95 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
96 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
wdenk359733b2003-03-31 17:27:09 +000097#endif
98
99}
100
101/*
102 * Initialize higher level parts of cpu
103 */
104int cpu_init_r (void)
105{
Wolfgang Denka1be4762008-05-20 16:00:29 +0200106 /* Nothing to do at the moment */
wdenk359733b2003-03-31 17:27:09 +0000107 return (0);
108}