Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / b54835158ee014998c9d9a036053987ac215e40e / . / arch / x86 / dts / dfi-bt700.dtsi
blob: 75ee6ade7c16e6e18a515600bb8b93b294e41217 [file] [log] [blame]
Stefan Roese312dc932016-08-15 13:50:49 +0200[diff] [blame]1/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <dt-bindings/gpio/x86-gpio.h>
9#include <dt-bindings/interrupt-router/intel-irq.h>
10
11#include "skeleton.dtsi"
12#include "rtc.dtsi"
13#include "tsc_timer.dtsi"
14
15/ {
16 config {
17 silent_console = <0>;
18 };
19
20 pch_pinctrl {
21 compatible = "intel,x86-pinctrl";
22 reg = <0 0>;
23
24 /* Add UART1 PAD configuration (SIO HS-UART) */
25 uart1_txd@0 {
26 pad-offset = <0x10>;
27 mode-func = <1>;
28 };
29
30 uart1_rxd@0 {
31 pad-offset = <0x20>;
32 mode-func = <1>;
33 };
34
35 /*
36 * As of today, the latest version FSP (gold4) for BayTrail
37 * misses the PAD configuration of the SD controller's Card
38 * Detect signal. The default PAD value for the CD pin sets
39 * the pin to work in GPIO mode, which causes card detect
40 * status cannot be reflected by the Present State register
41 * in the SD controller (bit 16 & bit 18 are always zero).
42 *
43 * Configure this pin to function 1 (SD controller).
44 */
45 sdmmc3_cd@0 {
46 pad-offset = <0x3a0>;
47 mode-func = <1>;
48 };
49 };
50
51 chosen {
52 stdout-path = "/serial";
53 };
54
55 cpus {
56 #address-cells = <1>;
57 #size-cells = <0>;
58
59 cpu@0 {
60 device_type = "cpu";
61 compatible = "intel,baytrail-cpu";
62 reg = <0>;
63 intel,apic-id = <0>;
64 };
65
66 cpu@1 {
67 device_type = "cpu";
68 compatible = "intel,baytrail-cpu";
69 reg = <1>;
70 intel,apic-id = <2>;
71 };
72
73 cpu@2 {
74 device_type = "cpu";
75 compatible = "intel,baytrail-cpu";
76 reg = <2>;
77 intel,apic-id = <4>;
78 };
79
80 cpu@3 {
81 device_type = "cpu";
82 compatible = "intel,baytrail-cpu";
83 reg = <3>;
84 intel,apic-id = <6>;
85 };
86 };
87
88 pci {
89 compatible = "intel,pci-baytrail", "pci-x86";
90 #address-cells = <3>;
91 #size-cells = <2>;
92 u-boot,dm-pre-reloc;
93 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
94 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
95 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
96
97 pciuart0: uart@1e,3 {
98 compatible = "pci8086,0f0a.00",
99 "pci8086,0f0a",
100 "pciclass,070002",
101 "pciclass,0700",
102 "ns16550";
103 u-boot,dm-pre-reloc;
104 reg = <0x0200f310 0x0 0x0 0x0 0x0>;
105 reg-shift = <2>;
106 clock-frequency = <58982400>;
107 current-speed = <115200>;
108 };
109
110 pch@1f,0 {
111 reg = <0x0000f800 0 0 0 0>;
112 compatible = "pci8086,0f1c", "intel,pch9";
113 #address-cells = <1>;
114 #size-cells = <1>;
115
116 irq-router {
117 compatible = "intel,irq-router";
118 intel,pirq-config = "ibase";
119 intel,ibase-offset = <0x50>;
120 intel,actl-addr = <0>;
121 intel,pirq-link = <8 8>;
122 intel,pirq-mask = <0xdee0>;
123 intel,pirq-routing = <
124 /* BayTrail PCI devices */
125 PCI_BDF(0, 2, 0) INTA PIRQA
126 PCI_BDF(0, 3, 0) INTA PIRQA
127 PCI_BDF(0, 16, 0) INTA PIRQA
128 PCI_BDF(0, 17, 0) INTA PIRQA
129 PCI_BDF(0, 18, 0) INTA PIRQA
130 PCI_BDF(0, 19, 0) INTA PIRQA
131 PCI_BDF(0, 20, 0) INTA PIRQA
132 PCI_BDF(0, 21, 0) INTA PIRQA
133 PCI_BDF(0, 22, 0) INTA PIRQA
134 PCI_BDF(0, 23, 0) INTA PIRQA
135 PCI_BDF(0, 24, 0) INTA PIRQA
136 PCI_BDF(0, 24, 1) INTC PIRQC
137 PCI_BDF(0, 24, 2) INTD PIRQD
138 PCI_BDF(0, 24, 3) INTB PIRQB
139 PCI_BDF(0, 24, 4) INTA PIRQA
140 PCI_BDF(0, 24, 5) INTC PIRQC
141 PCI_BDF(0, 24, 6) INTD PIRQD
142 PCI_BDF(0, 24, 7) INTB PIRQB
143 PCI_BDF(0, 26, 0) INTA PIRQA
144 PCI_BDF(0, 27, 0) INTA PIRQA
145 PCI_BDF(0, 28, 0) INTA PIRQA
146 PCI_BDF(0, 28, 1) INTB PIRQB
147 PCI_BDF(0, 28, 2) INTC PIRQC
148 PCI_BDF(0, 28, 3) INTD PIRQD
149 PCI_BDF(0, 29, 0) INTA PIRQA
150 PCI_BDF(0, 30, 0) INTA PIRQA
151 PCI_BDF(0, 30, 1) INTD PIRQD
152 PCI_BDF(0, 30, 2) INTB PIRQB
153 PCI_BDF(0, 30, 3) INTC PIRQC
154 PCI_BDF(0, 30, 4) INTD PIRQD
155 PCI_BDF(0, 30, 5) INTB PIRQB
156 PCI_BDF(0, 31, 3) INTB PIRQB
157
158 /*
159 * PCIe root ports downstream
160 * interrupts
161 */
162 PCI_BDF(1, 0, 0) INTA PIRQA
163 PCI_BDF(1, 0, 0) INTB PIRQB
164 PCI_BDF(1, 0, 0) INTC PIRQC
165 PCI_BDF(1, 0, 0) INTD PIRQD
166 PCI_BDF(2, 0, 0) INTA PIRQB
167 PCI_BDF(2, 0, 0) INTB PIRQC
168 PCI_BDF(2, 0, 0) INTC PIRQD
169 PCI_BDF(2, 0, 0) INTD PIRQA
170 PCI_BDF(3, 0, 0) INTA PIRQC
171 PCI_BDF(3, 0, 0) INTB PIRQD
172 PCI_BDF(3, 0, 0) INTC PIRQA
173 PCI_BDF(3, 0, 0) INTD PIRQB
174 PCI_BDF(4, 0, 0) INTA PIRQD
175 PCI_BDF(4, 0, 0) INTB PIRQA
176 PCI_BDF(4, 0, 0) INTC PIRQB
177 PCI_BDF(4, 0, 0) INTD PIRQC
178 >;
179 };
180
181 spi: spi {
182 #address-cells = <1>;
183 #size-cells = <0>;
184 compatible = "intel,ich9-spi";
185 spi-flash@0 {
186 #address-cells = <1>;
187 #size-cells = <1>;
188 reg = <0>;
189 compatible = "stmicro,n25q064a",
190 "spi-flash";
191 memory-map = <0xff800000 0x00800000>;
192 rw-mrc-cache {
193 label = "rw-mrc-cache";
194 reg = <0x006f0000 0x00010000>;
195 };
196 };
197 };
198
199 gpioa {
200 compatible = "intel,ich6-gpio";
201 u-boot,dm-pre-reloc;
202 reg = <0 0x20>;
203 bank-name = "A";
204 };
205
206 gpiob {
207 compatible = "intel,ich6-gpio";
208 u-boot,dm-pre-reloc;
209 reg = <0x20 0x20>;
210 bank-name = "B";
211 };
212
213 gpioc {
214 compatible = "intel,ich6-gpio";
215 u-boot,dm-pre-reloc;
216 reg = <0x40 0x20>;
217 bank-name = "C";
218 };
219
220 gpiod {
221 compatible = "intel,ich6-gpio";
222 u-boot,dm-pre-reloc;
223 reg = <0x60 0x20>;
224 bank-name = "D";
225 };
226
227 gpioe {
228 compatible = "intel,ich6-gpio";
229 u-boot,dm-pre-reloc;
230 reg = <0x80 0x20>;
231 bank-name = "E";
232 };
233
234 gpiof {
235 compatible = "intel,ich6-gpio";
236 u-boot,dm-pre-reloc;
237 reg = <0xA0 0x20>;
238 bank-name = "F";
239 };
240 };
241 };
242
243 fsp {
244 compatible = "intel,baytrail-fsp";
245 fsp,mrc-init-tseg-size = <0>;
246 fsp,mrc-init-mmio-size = <0x800>;
247 fsp,mrc-init-spd-addr1 = <0xa0>;
248 fsp,mrc-init-spd-addr2 = <0xa2>;
249 fsp,emmc-boot-mode = <1>;
250 fsp,enable-sdio;
251 fsp,enable-sdcard;
252 fsp,enable-hsuart0;
253 fsp,enable-hsuart1;
254 fsp,enable-spi;
255 fsp,enable-sata;
256 fsp,sata-mode = <1>;
257 fsp,enable-lpe;
258 fsp,lpss-sio-enable-pci-mode;
259 fsp,enable-dma0;
260 fsp,enable-dma1;
261 fsp,enable-i2c0;
262 fsp,enable-i2c1;
263 fsp,enable-i2c2;
264 fsp,enable-i2c3;
265 fsp,enable-i2c4;
266 fsp,enable-i2c5;
267 fsp,enable-i2c6;
268 fsp,enable-pwm0;
269 fsp,enable-pwm1;
270 fsp,igd-dvmt50-pre-alloc = <2>;
271 fsp,aperture-size = <2>;
272 fsp,gtt-size = <2>;
273 fsp,scc-enable-pci-mode;
274 fsp,os-selection = <4>;
275 fsp,emmc45-ddr50-enabled;
276 fsp,emmc45-retune-timer-value = <8>;
277 fsp,enable-igd;
278 fsp,enable-memory-down;
279 fsp,memory-down-params {
280 compatible = "intel,baytrail-fsp-mdp";
281 fsp,dram-speed = <2>; /* 2=1333MHz */
282 fsp,dram-type = <1>; /* 1=DDR3L */
283 fsp,dimm-0-enable;
284 fsp,dimm-width = <1>; /* 1=x16, 2=x32 */
285 fsp,dimm-density = <3>; /* 3=8Gbit */
286 fsp,dimm-bus-width = <3>; /* 3=64bits */
287 fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */
288
289 /* These following values might need a re-visit */
290 fsp,dimm-tcl = <8>;
291 fsp,dimm-trpt-rcd = <8>;
292 fsp,dimm-twr = <8>;
293 fsp,dimm-twtr = <4>;
294 fsp,dimm-trrd = <6>;
295 fsp,dimm-trtp = <4>;
296 fsp,dimm-tfaw = <22>;
297 };
298 };
299
300 microcode {
301 update@0 {
302#include "microcode/m0130673325.dtsi"
303 };
304 update@1 {
305#include "microcode/m0130679907.dtsi"
306 };
307 };
308};