blob: 66ddf8d655bed9132584957c75cfb1a16ea9dcc5 [file] [log] [blame]
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +08001/*
2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+ X11
5 */
6
7/dts-v1/;
8#include "rk3288-fennec.dtsi"
9
10/ {
11 model = "Rockchip RK3288 Fennec Board";
12 compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
13
14 chosen {
15 stdout-path = &uart2;
16 };
17};
18
19&dmc {
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +080020 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
21 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
22 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
23 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
24 0x8 0x1f4>;
25 rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
26 0x0 0xc3 0x6 0x2>;
jk.kernel@gmail.comb1aeb092016-07-26 18:28:29 +080027 rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
28};
29
30&pinctrl {
31 u-boot,dm-pre-reloc;
32};
33
34&pwm1 {
35 status = "okay";
36};
37
38&uart2 {
39 u-boot,dm-pre-reloc;
40 reg-shift = <2>;
41};
42
43&sdmmc {
44 u-boot,dm-pre-reloc;
45};
46
47&emmc {
48 u-boot,dm-pre-reloc;
49};
50
51&gpio3 {
52 u-boot,dm-pre-reloc;
53};
54
55&gpio8 {
56 u-boot,dm-pre-reloc;
57};