| Chris Zankel | 1387dab | 2016-08-10 18:36:44 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Miscellaneous assembly functions. |
| 3 | * |
| 4 | * Copyright (C) 2001 - 2007 Tensilica Inc. |
| 5 | * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. |
| 6 | * |
| 7 | * Chris Zankel <chris@zankel.net> |
| 8 | * |
| 9 | * SPDX-License-Identifier: GPL-2.0+ |
| 10 | */ |
| 11 | |
| 12 | |
| 13 | #include <linux/linkage.h> |
| 14 | #include <asm/asmmacro.h> |
| 15 | #include <asm/cacheasm.h> |
| 16 | |
| 17 | /* |
| 18 | * void __invalidate_icache_page(ulong start) |
| 19 | */ |
| 20 | |
| 21 | ENTRY(__invalidate_icache_page) |
| 22 | |
| 23 | abi_entry |
| 24 | |
| 25 | ___invalidate_icache_page a2 a3 |
| 26 | isync |
| 27 | |
| 28 | abi_ret |
| 29 | |
| 30 | ENDPROC(__invalidate_icache_page) |
| 31 | |
| 32 | /* |
| 33 | * void __invalidate_dcache_page(ulong start) |
| 34 | */ |
| 35 | |
| 36 | ENTRY(__invalidate_dcache_page) |
| 37 | |
| 38 | abi_entry |
| 39 | |
| 40 | ___invalidate_dcache_page a2 a3 |
| 41 | dsync |
| 42 | |
| 43 | abi_ret |
| 44 | |
| 45 | ENDPROC(__invalidate_dcache_page) |
| 46 | |
| 47 | /* |
| 48 | * void __flush_invalidate_dcache_page(ulong start) |
| 49 | */ |
| 50 | |
| 51 | ENTRY(__flush_invalidate_dcache_page) |
| 52 | |
| 53 | abi_entry |
| 54 | |
| 55 | ___flush_invalidate_dcache_page a2 a3 |
| 56 | |
| 57 | dsync |
| 58 | abi_ret |
| 59 | |
| 60 | ENDPROC(__flush_invalidate_dcache_page) |
| 61 | |
| 62 | /* |
| 63 | * void __flush_dcache_page(ulong start) |
| 64 | */ |
| 65 | |
| 66 | ENTRY(__flush_dcache_page) |
| 67 | |
| 68 | abi_entry |
| 69 | |
| 70 | ___flush_dcache_page a2 a3 |
| 71 | |
| 72 | dsync |
| 73 | abi_ret |
| 74 | |
| 75 | ENDPROC(__flush_dcache_page) |
| 76 | |
| 77 | /* |
| 78 | * void __invalidate_icache_range(ulong start, ulong size) |
| 79 | */ |
| 80 | |
| 81 | ENTRY(__invalidate_icache_range) |
| 82 | |
| 83 | abi_entry |
| 84 | |
| 85 | ___invalidate_icache_range a2 a3 a4 |
| 86 | isync |
| 87 | |
| 88 | abi_ret |
| 89 | |
| 90 | ENDPROC(__invalidate_icache_range) |
| 91 | |
| 92 | /* |
| 93 | * void __flush_invalidate_dcache_range(ulong start, ulong size) |
| 94 | */ |
| 95 | |
| 96 | ENTRY(__flush_invalidate_dcache_range) |
| 97 | |
| 98 | abi_entry |
| 99 | |
| 100 | ___flush_invalidate_dcache_range a2 a3 a4 |
| 101 | dsync |
| 102 | |
| 103 | abi_ret |
| 104 | |
| 105 | ENDPROC(__flush_invalidate_dcache_range) |
| 106 | |
| 107 | /* |
| 108 | * void _flush_dcache_range(ulong start, ulong size) |
| 109 | */ |
| 110 | |
| 111 | ENTRY(__flush_dcache_range) |
| 112 | |
| 113 | abi_entry |
| 114 | |
| 115 | ___flush_dcache_range a2 a3 a4 |
| 116 | dsync |
| 117 | |
| 118 | abi_ret |
| 119 | |
| 120 | ENDPROC(__flush_dcache_range) |
| 121 | |
| 122 | /* |
| 123 | * void _invalidate_dcache_range(ulong start, ulong size) |
| 124 | */ |
| 125 | |
| 126 | ENTRY(__invalidate_dcache_range) |
| 127 | |
| 128 | abi_entry |
| 129 | |
| 130 | ___invalidate_dcache_range a2 a3 a4 |
| 131 | |
| 132 | abi_ret |
| 133 | |
| 134 | ENDPROC(__invalidate_dcache_range) |
| 135 | |
| 136 | /* |
| 137 | * void _invalidate_icache_all(void) |
| 138 | */ |
| 139 | |
| 140 | ENTRY(__invalidate_icache_all) |
| 141 | |
| 142 | abi_entry |
| 143 | |
| 144 | ___invalidate_icache_all a2 a3 |
| 145 | isync |
| 146 | |
| 147 | abi_ret |
| 148 | |
| 149 | ENDPROC(__invalidate_icache_all) |
| 150 | |
| 151 | /* |
| 152 | * void _flush_invalidate_dcache_all(void) |
| 153 | */ |
| 154 | |
| 155 | ENTRY(__flush_invalidate_dcache_all) |
| 156 | |
| 157 | abi_entry |
| 158 | |
| 159 | ___flush_invalidate_dcache_all a2 a3 |
| 160 | dsync |
| 161 | |
| 162 | abi_ret |
| 163 | |
| 164 | ENDPROC(__flush_invalidate_dcache_all) |
| 165 | |
| 166 | /* |
| 167 | * void _invalidate_dcache_all(void) |
| 168 | */ |
| 169 | |
| 170 | ENTRY(__invalidate_dcache_all) |
| 171 | |
| 172 | abi_entry |
| 173 | |
| 174 | ___invalidate_dcache_all a2 a3 |
| 175 | dsync |
| 176 | |
| 177 | abi_ret |
| 178 | |
| 179 | ENDPROC(__invalidate_dcache_all) |