Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 2 | /* |
Vabhav Sharma | a8f78c6 | 2019-01-31 12:08:10 +0000 | [diff] [blame] | 3 | * Copyright 2019 NXP |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 4 | * Copyright 2013 Freescale Semiconductor, Inc. |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Tom Rini | 8c70baa | 2021-12-14 13:36:40 -0500 | [diff] [blame] | 8 | #include <clock_legacy.h> |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 9 | #include <clk.h> |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 10 | #include <dm.h> |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 11 | #include <fsl_lpuart.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 12 | #include <log.h> |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 13 | #include <watchdog.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 14 | #include <asm/global_data.h> |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 15 | #include <asm/io.h> |
| 16 | #include <serial.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 17 | #include <dm/device_compat.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 18 | #include <linux/bitops.h> |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 19 | #include <linux/compiler.h> |
| 20 | #include <asm/arch/imx-regs.h> |
| 21 | #include <asm/arch/clock.h> |
| 22 | |
Bin Meng | a8cc172 | 2016-01-13 19:39:01 -0800 | [diff] [blame] | 23 | #define US1_TDRE (1 << 7) |
| 24 | #define US1_RDRF (1 << 5) |
| 25 | #define US1_OR (1 << 3) |
| 26 | #define UC2_TE (1 << 3) |
| 27 | #define UC2_RE (1 << 2) |
| 28 | #define CFIFO_TXFLUSH (1 << 7) |
| 29 | #define CFIFO_RXFLUSH (1 << 6) |
| 30 | #define SFIFO_RXOF (1 << 2) |
| 31 | #define SFIFO_RXUF (1 << 0) |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 32 | |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 33 | #define STAT_LBKDIF (1 << 31) |
| 34 | #define STAT_RXEDGIF (1 << 30) |
| 35 | #define STAT_TDRE (1 << 23) |
| 36 | #define STAT_RDRF (1 << 21) |
| 37 | #define STAT_IDLE (1 << 20) |
| 38 | #define STAT_OR (1 << 19) |
| 39 | #define STAT_NF (1 << 18) |
| 40 | #define STAT_FE (1 << 17) |
| 41 | #define STAT_PF (1 << 16) |
| 42 | #define STAT_MA1F (1 << 15) |
| 43 | #define STAT_MA2F (1 << 14) |
| 44 | #define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \ |
Bin Meng | a8cc172 | 2016-01-13 19:39:01 -0800 | [diff] [blame] | 45 | STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F) |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 46 | |
| 47 | #define CTRL_TE (1 << 19) |
| 48 | #define CTRL_RE (1 << 18) |
| 49 | |
Ye Li | a2aedcb | 2018-10-18 14:28:32 +0200 | [diff] [blame] | 50 | #define FIFO_RXFLUSH BIT(14) |
| 51 | #define FIFO_TXFLUSH BIT(15) |
| 52 | #define FIFO_TXSIZE_MASK 0x70 |
| 53 | #define FIFO_TXSIZE_OFF 4 |
| 54 | #define FIFO_RXSIZE_MASK 0x7 |
| 55 | #define FIFO_RXSIZE_OFF 0 |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 56 | #define FIFO_TXFE 0x80 |
Giulio Benetti | 5eaa97e | 2020-01-10 15:51:43 +0100 | [diff] [blame] | 57 | #if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT) |
Peng Fan | b7f9ea9 | 2018-10-18 14:28:31 +0200 | [diff] [blame] | 58 | #define FIFO_RXFE 0x08 |
| 59 | #else |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 60 | #define FIFO_RXFE 0x40 |
Peng Fan | b7f9ea9 | 2018-10-18 14:28:31 +0200 | [diff] [blame] | 61 | #endif |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 62 | |
Ye Li | a2aedcb | 2018-10-18 14:28:32 +0200 | [diff] [blame] | 63 | #define WATER_TXWATER_OFF 0 |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 64 | #define WATER_RXWATER_OFF 16 |
| 65 | |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 66 | DECLARE_GLOBAL_DATA_PTR; |
| 67 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 68 | #define LPUART_FLAG_REGMAP_32BIT_REG BIT(0) |
| 69 | #define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1) |
| 70 | |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 71 | enum lpuart_devtype { |
| 72 | DEV_VF610 = 1, |
| 73 | DEV_LS1021A, |
Peng Fan | b7f9ea9 | 2018-10-18 14:28:31 +0200 | [diff] [blame] | 74 | DEV_MX7ULP, |
Giulio Benetti | 5eaa97e | 2020-01-10 15:51:43 +0100 | [diff] [blame] | 75 | DEV_IMX8, |
| 76 | DEV_IMXRT, |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 77 | }; |
| 78 | |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 79 | struct lpuart_serial_plat { |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 80 | void *reg; |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 81 | enum lpuart_devtype devtype; |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 82 | ulong flags; |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 83 | }; |
| 84 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 85 | static void lpuart_read32(u32 flags, u32 *addr, u32 *val) |
| 86 | { |
| 87 | if (flags & LPUART_FLAG_REGMAP_32BIT_REG) { |
| 88 | if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG) |
| 89 | *(u32 *)val = in_be32(addr); |
| 90 | else |
| 91 | *(u32 *)val = in_le32(addr); |
| 92 | } |
| 93 | } |
| 94 | |
| 95 | static void lpuart_write32(u32 flags, u32 *addr, u32 val) |
| 96 | { |
| 97 | if (flags & LPUART_FLAG_REGMAP_32BIT_REG) { |
| 98 | if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG) |
| 99 | out_be32(addr, val); |
| 100 | else |
| 101 | out_le32(addr, val); |
| 102 | } |
| 103 | } |
| 104 | |
| 105 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 106 | u32 __weak get_lpuart_clk(void) |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 107 | { |
Tom Rini | 8c70baa | 2021-12-14 13:36:40 -0500 | [diff] [blame] | 108 | return get_board_sys_clk(); |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 109 | } |
| 110 | |
Ye Li | 86cf699 | 2019-07-11 03:33:34 +0000 | [diff] [blame] | 111 | #if CONFIG_IS_ENABLED(CLK) |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 112 | static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk) |
| 113 | { |
| 114 | struct clk per_clk; |
| 115 | ulong rate; |
| 116 | int ret; |
| 117 | |
| 118 | ret = clk_get_by_name(dev, "per", &per_clk); |
| 119 | if (ret) { |
| 120 | dev_err(dev, "Failed to get per clk: %d\n", ret); |
| 121 | return ret; |
| 122 | } |
| 123 | |
| 124 | rate = clk_get_rate(&per_clk); |
| 125 | if ((long)rate <= 0) { |
| 126 | dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate); |
| 127 | return ret; |
| 128 | } |
| 129 | *clk = rate; |
| 130 | return 0; |
| 131 | } |
| 132 | #else |
| 133 | static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk) |
| 134 | { return -ENOSYS; } |
| 135 | #endif |
| 136 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 137 | static bool is_lpuart32(struct udevice *dev) |
| 138 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 139 | struct lpuart_serial_plat *plat = dev_get_plat(dev); |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 140 | |
| 141 | return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG; |
| 142 | } |
| 143 | |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 144 | static void _lpuart_serial_setbrg(struct udevice *dev, |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 145 | int baudrate) |
| 146 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 147 | struct lpuart_serial_plat *plat = dev_get_plat(dev); |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 148 | struct lpuart_fsl *base = plat->reg; |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 149 | u32 clk; |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 150 | u16 sbr; |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 151 | int ret; |
| 152 | |
Ye Li | 86cf699 | 2019-07-11 03:33:34 +0000 | [diff] [blame] | 153 | if (CONFIG_IS_ENABLED(CLK)) { |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 154 | ret = get_lpuart_clk_rate(dev, &clk); |
| 155 | if (ret) |
| 156 | return; |
| 157 | } else { |
| 158 | clk = get_lpuart_clk(); |
| 159 | } |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 160 | |
Bin Meng | 6338fbd | 2016-01-13 19:39:03 -0800 | [diff] [blame] | 161 | sbr = (u16)(clk / (16 * baudrate)); |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 162 | |
Bin Meng | a8cc172 | 2016-01-13 19:39:01 -0800 | [diff] [blame] | 163 | /* place adjustment later - n/32 BRFA */ |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 164 | __raw_writeb(sbr >> 8, &base->ubdh); |
| 165 | __raw_writeb(sbr & 0xff, &base->ubdl); |
| 166 | } |
| 167 | |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 168 | static int _lpuart_serial_getc(struct lpuart_serial_plat *plat) |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 169 | { |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 170 | struct lpuart_fsl *base = plat->reg; |
Pali Rohár | 241f12d | 2022-12-11 00:31:21 +0100 | [diff] [blame] | 171 | if (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR))) |
| 172 | return -EAGAIN; |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 173 | |
Stefan Agner | 2448291 | 2014-08-19 17:54:27 +0200 | [diff] [blame] | 174 | barrier(); |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 175 | |
| 176 | return __raw_readb(&base->ud); |
| 177 | } |
| 178 | |
Pali Rohár | 241f12d | 2022-12-11 00:31:21 +0100 | [diff] [blame] | 179 | static int _lpuart_serial_putc(struct lpuart_serial_plat *plat, |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 180 | const char c) |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 181 | { |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 182 | struct lpuart_fsl *base = plat->reg; |
| 183 | |
Pali Rohár | 241f12d | 2022-12-11 00:31:21 +0100 | [diff] [blame] | 184 | if (!(__raw_readb(&base->us1) & US1_TDRE)) |
| 185 | return -EAGAIN; |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 186 | |
| 187 | __raw_writeb(c, &base->ud); |
Pali Rohár | 241f12d | 2022-12-11 00:31:21 +0100 | [diff] [blame] | 188 | return 0; |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 189 | } |
| 190 | |
Bin Meng | a8cc172 | 2016-01-13 19:39:01 -0800 | [diff] [blame] | 191 | /* Test whether a character is in the RX buffer */ |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 192 | static int _lpuart_serial_tstc(struct lpuart_serial_plat *plat) |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 193 | { |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 194 | struct lpuart_fsl *base = plat->reg; |
| 195 | |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 196 | if (__raw_readb(&base->urcfifo) == 0) |
| 197 | return 0; |
| 198 | |
| 199 | return 1; |
| 200 | } |
| 201 | |
| 202 | /* |
| 203 | * Initialise the serial port with the given baudrate. The settings |
| 204 | * are always 8 data bits, no parity, 1 stop bit, no start bits. |
| 205 | */ |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 206 | static int _lpuart_serial_init(struct udevice *dev) |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 207 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 208 | struct lpuart_serial_plat *plat = dev_get_plat(dev); |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 209 | struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg; |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 210 | u8 ctrl; |
| 211 | |
| 212 | ctrl = __raw_readb(&base->uc2); |
| 213 | ctrl &= ~UC2_RE; |
| 214 | ctrl &= ~UC2_TE; |
| 215 | __raw_writeb(ctrl, &base->uc2); |
| 216 | |
| 217 | __raw_writeb(0, &base->umodem); |
| 218 | __raw_writeb(0, &base->uc1); |
| 219 | |
Stefan Agner | 190f1d2 | 2014-08-19 17:54:28 +0200 | [diff] [blame] | 220 | /* Disable FIFO and flush buffer */ |
| 221 | __raw_writeb(0x0, &base->upfifo); |
| 222 | __raw_writeb(0x0, &base->utwfifo); |
| 223 | __raw_writeb(0x1, &base->urwfifo); |
| 224 | __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo); |
| 225 | |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 226 | /* provide data bits, parity, stop bit, etc */ |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 227 | _lpuart_serial_setbrg(dev, gd->baudrate); |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 228 | |
| 229 | __raw_writeb(UC2_RE | UC2_TE, &base->uc2); |
| 230 | |
| 231 | return 0; |
| 232 | } |
| 233 | |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 234 | static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev, |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 235 | int baudrate) |
| 236 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 237 | struct lpuart_serial_plat *plat = dev_get_plat(dev); |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 238 | struct lpuart_fsl_reg32 *base = plat->reg; |
| 239 | u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 240 | u32 clk; |
| 241 | int ret; |
| 242 | |
Ye Li | 86cf699 | 2019-07-11 03:33:34 +0000 | [diff] [blame] | 243 | if (CONFIG_IS_ENABLED(CLK)) { |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 244 | ret = get_lpuart_clk_rate(dev, &clk); |
| 245 | if (ret) |
| 246 | return; |
| 247 | } else { |
| 248 | clk = get_lpuart_clk(); |
| 249 | } |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 250 | |
| 251 | baud_diff = baudrate; |
| 252 | osr = 0; |
| 253 | sbr = 0; |
| 254 | |
| 255 | for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { |
| 256 | tmp_sbr = (clk / (baudrate * tmp_osr)); |
| 257 | |
| 258 | if (tmp_sbr == 0) |
| 259 | tmp_sbr = 1; |
| 260 | |
| 261 | /*calculate difference in actual buad w/ current values */ |
| 262 | tmp_diff = (clk / (tmp_osr * tmp_sbr)); |
| 263 | tmp_diff = tmp_diff - baudrate; |
| 264 | |
| 265 | /* select best values between sbr and sbr+1 */ |
| 266 | if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) { |
| 267 | tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1))); |
| 268 | tmp_sbr++; |
| 269 | } |
| 270 | |
| 271 | if (tmp_diff <= baud_diff) { |
| 272 | baud_diff = tmp_diff; |
| 273 | osr = tmp_osr; |
| 274 | sbr = tmp_sbr; |
| 275 | } |
| 276 | } |
| 277 | |
| 278 | /* |
| 279 | * TODO: handle buadrate outside acceptable rate |
| 280 | * if (baudDiff > ((config->baudRate_Bps / 100) * 3)) |
| 281 | * { |
| 282 | * Unacceptable baud rate difference of more than 3% |
| 283 | * return kStatus_LPUART_BaudrateNotSupport; |
| 284 | * } |
| 285 | */ |
| 286 | tmp = in_le32(&base->baud); |
| 287 | |
| 288 | if ((osr > 3) && (osr < 8)) |
| 289 | tmp |= LPUART_BAUD_BOTHEDGE_MASK; |
| 290 | |
| 291 | tmp &= ~LPUART_BAUD_OSR_MASK; |
| 292 | tmp |= LPUART_BAUD_OSR(osr-1); |
| 293 | |
| 294 | tmp &= ~LPUART_BAUD_SBR_MASK; |
| 295 | tmp |= LPUART_BAUD_SBR(sbr); |
| 296 | |
| 297 | /* explicitly disable 10 bit mode & set 1 stop bit */ |
| 298 | tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK); |
| 299 | |
| 300 | out_le32(&base->baud, tmp); |
| 301 | } |
| 302 | |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 303 | static void _lpuart32_serial_setbrg(struct udevice *dev, |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 304 | int baudrate) |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 305 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 306 | struct lpuart_serial_plat *plat = dev_get_plat(dev); |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 307 | struct lpuart_fsl_reg32 *base = plat->reg; |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 308 | u32 clk; |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 309 | u32 sbr; |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 310 | int ret; |
| 311 | |
Ye Li | 86cf699 | 2019-07-11 03:33:34 +0000 | [diff] [blame] | 312 | if (CONFIG_IS_ENABLED(CLK)) { |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 313 | ret = get_lpuart_clk_rate(dev, &clk); |
| 314 | if (ret) |
| 315 | return; |
| 316 | } else { |
| 317 | clk = get_lpuart_clk(); |
| 318 | } |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 319 | |
Bin Meng | 6338fbd | 2016-01-13 19:39:03 -0800 | [diff] [blame] | 320 | sbr = (clk / (16 * baudrate)); |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 321 | |
Bin Meng | a8cc172 | 2016-01-13 19:39:01 -0800 | [diff] [blame] | 322 | /* place adjustment later - n/32 BRFA */ |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 323 | lpuart_write32(plat->flags, &base->baud, sbr); |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 324 | } |
| 325 | |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 326 | static int _lpuart32_serial_getc(struct lpuart_serial_plat *plat) |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 327 | { |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 328 | struct lpuart_fsl_reg32 *base = plat->reg; |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 329 | u32 stat, val; |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 330 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 331 | lpuart_read32(plat->flags, &base->stat, &stat); |
Pali Rohár | 241f12d | 2022-12-11 00:31:21 +0100 | [diff] [blame] | 332 | if ((stat & STAT_RDRF) == 0) { |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 333 | lpuart_write32(plat->flags, &base->stat, STAT_FLAGS); |
Pali Rohár | 241f12d | 2022-12-11 00:31:21 +0100 | [diff] [blame] | 334 | return -EAGAIN; |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 335 | } |
| 336 | |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 337 | lpuart_read32(plat->flags, &base->data, &val); |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 338 | |
Sriram Dash | 32cf46c | 2018-01-10 11:57:14 +0530 | [diff] [blame] | 339 | lpuart_read32(plat->flags, &base->stat, &stat); |
| 340 | if (stat & STAT_OR) |
| 341 | lpuart_write32(plat->flags, &base->stat, STAT_OR); |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 342 | |
| 343 | return val & 0x3ff; |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 344 | } |
| 345 | |
Pali Rohár | 241f12d | 2022-12-11 00:31:21 +0100 | [diff] [blame] | 346 | static int _lpuart32_serial_putc(struct lpuart_serial_plat *plat, |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 347 | const char c) |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 348 | { |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 349 | struct lpuart_fsl_reg32 *base = plat->reg; |
| 350 | u32 stat; |
| 351 | |
Pali Rohár | 241f12d | 2022-12-11 00:31:21 +0100 | [diff] [blame] | 352 | lpuart_read32(plat->flags, &base->stat, &stat); |
| 353 | if (!(stat & STAT_TDRE)) |
| 354 | return -EAGAIN; |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 355 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 356 | lpuart_write32(plat->flags, &base->data, c); |
Pali Rohár | 241f12d | 2022-12-11 00:31:21 +0100 | [diff] [blame] | 357 | return 0; |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 358 | } |
| 359 | |
Bin Meng | a8cc172 | 2016-01-13 19:39:01 -0800 | [diff] [blame] | 360 | /* Test whether a character is in the RX buffer */ |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 361 | static int _lpuart32_serial_tstc(struct lpuart_serial_plat *plat) |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 362 | { |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 363 | struct lpuart_fsl_reg32 *base = plat->reg; |
| 364 | u32 water; |
| 365 | |
| 366 | lpuart_read32(plat->flags, &base->water, &water); |
| 367 | |
| 368 | if ((water >> 24) == 0) |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 369 | return 0; |
| 370 | |
| 371 | return 1; |
| 372 | } |
| 373 | |
| 374 | /* |
| 375 | * Initialise the serial port with the given baudrate. The settings |
| 376 | * are always 8 data bits, no parity, 1 stop bit, no start bits. |
| 377 | */ |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 378 | static int _lpuart32_serial_init(struct udevice *dev) |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 379 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 380 | struct lpuart_serial_plat *plat = dev_get_plat(dev); |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 381 | struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg; |
Ye Li | a2aedcb | 2018-10-18 14:28:32 +0200 | [diff] [blame] | 382 | u32 val, tx_fifo_size; |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 383 | |
Ye Li | a2aedcb | 2018-10-18 14:28:32 +0200 | [diff] [blame] | 384 | lpuart_read32(plat->flags, &base->ctrl, &val); |
| 385 | val &= ~CTRL_RE; |
| 386 | val &= ~CTRL_TE; |
| 387 | lpuart_write32(plat->flags, &base->ctrl, val); |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 388 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 389 | lpuart_write32(plat->flags, &base->modir, 0); |
Ye Li | a2aedcb | 2018-10-18 14:28:32 +0200 | [diff] [blame] | 390 | |
| 391 | lpuart_read32(plat->flags, &base->fifo, &val); |
| 392 | tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF; |
| 393 | /* Set the TX water to half of FIFO size */ |
| 394 | if (tx_fifo_size > 1) |
| 395 | tx_fifo_size = tx_fifo_size >> 1; |
| 396 | |
| 397 | /* Set RX water to 0, to be triggered by any receive data */ |
| 398 | lpuart_write32(plat->flags, &base->water, |
| 399 | (tx_fifo_size << WATER_TXWATER_OFF)); |
| 400 | |
| 401 | /* Enable TX and RX FIFO */ |
| 402 | val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH); |
| 403 | lpuart_write32(plat->flags, &base->fifo, val); |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 404 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 405 | lpuart_write32(plat->flags, &base->match, 0); |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 406 | |
Giulio Benetti | 5eaa97e | 2020-01-10 15:51:43 +0100 | [diff] [blame] | 407 | if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 || |
| 408 | plat->devtype == DEV_IMXRT) { |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 409 | _lpuart32_serial_setbrg_7ulp(dev, gd->baudrate); |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 410 | } else { |
| 411 | /* provide data bits, parity, stop bit, etc */ |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 412 | _lpuart32_serial_setbrg(dev, gd->baudrate); |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 413 | } |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 414 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 415 | lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE); |
Jingchang Lu | 4a7154e | 2014-09-05 13:52:47 +0800 | [diff] [blame] | 416 | |
| 417 | return 0; |
| 418 | } |
| 419 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 420 | static int lpuart_serial_setbrg(struct udevice *dev, int baudrate) |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 421 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 422 | struct lpuart_serial_plat *plat = dev_get_plat(dev); |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 423 | |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 424 | if (is_lpuart32(dev)) { |
Giulio Benetti | 5eaa97e | 2020-01-10 15:51:43 +0100 | [diff] [blame] | 425 | if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 || |
| 426 | plat->devtype == DEV_IMXRT) |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 427 | _lpuart32_serial_setbrg_7ulp(dev, baudrate); |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 428 | else |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 429 | _lpuart32_serial_setbrg(dev, baudrate); |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 430 | } else { |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 431 | _lpuart_serial_setbrg(dev, baudrate); |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 432 | } |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 433 | |
| 434 | return 0; |
| 435 | } |
| 436 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 437 | static int lpuart_serial_getc(struct udevice *dev) |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 438 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 439 | struct lpuart_serial_plat *plat = dev_get_plat(dev); |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 440 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 441 | if (is_lpuart32(dev)) |
| 442 | return _lpuart32_serial_getc(plat); |
| 443 | |
| 444 | return _lpuart_serial_getc(plat); |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 445 | } |
| 446 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 447 | static int lpuart_serial_putc(struct udevice *dev, const char c) |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 448 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 449 | struct lpuart_serial_plat *plat = dev_get_plat(dev); |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 450 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 451 | if (is_lpuart32(dev)) |
Pali Rohár | 241f12d | 2022-12-11 00:31:21 +0100 | [diff] [blame] | 452 | return _lpuart32_serial_putc(plat, c); |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 453 | |
Pali Rohár | 241f12d | 2022-12-11 00:31:21 +0100 | [diff] [blame] | 454 | return _lpuart_serial_putc(plat, c); |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 455 | } |
| 456 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 457 | static int lpuart_serial_pending(struct udevice *dev, bool input) |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 458 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 459 | struct lpuart_serial_plat *plat = dev_get_plat(dev); |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 460 | struct lpuart_fsl *reg = plat->reg; |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 461 | struct lpuart_fsl_reg32 *reg32 = plat->reg; |
| 462 | u32 stat; |
| 463 | |
| 464 | if (is_lpuart32(dev)) { |
| 465 | if (input) { |
| 466 | return _lpuart32_serial_tstc(plat); |
| 467 | } else { |
| 468 | lpuart_read32(plat->flags, ®32->stat, &stat); |
| 469 | return stat & STAT_TDRE ? 0 : 1; |
| 470 | } |
| 471 | } |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 472 | |
| 473 | if (input) |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 474 | return _lpuart_serial_tstc(plat); |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 475 | else |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 476 | return __raw_readb(®->us1) & US1_TDRE ? 0 : 1; |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 477 | } |
| 478 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 479 | static int lpuart_serial_probe(struct udevice *dev) |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 480 | { |
Giulio Benetti | 0ad8b9c | 2020-01-10 15:47:05 +0100 | [diff] [blame] | 481 | #if CONFIG_IS_ENABLED(CLK) |
| 482 | struct clk per_clk; |
| 483 | int ret; |
| 484 | |
| 485 | ret = clk_get_by_name(dev, "per", &per_clk); |
| 486 | if (!ret) { |
| 487 | ret = clk_enable(&per_clk); |
| 488 | if (ret) { |
| 489 | dev_err(dev, "Failed to get per clk: %d\n", ret); |
| 490 | return ret; |
| 491 | } |
| 492 | } else { |
Giulio Benetti | 8bb8dcf | 2020-01-31 14:39:47 +0100 | [diff] [blame] | 493 | debug("%s: Failed to get per clk: %d\n", __func__, ret); |
Giulio Benetti | 0ad8b9c | 2020-01-10 15:47:05 +0100 | [diff] [blame] | 494 | } |
| 495 | #endif |
| 496 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 497 | if (is_lpuart32(dev)) |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 498 | return _lpuart32_serial_init(dev); |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 499 | else |
Peng Fan | 68e4563 | 2018-10-19 00:26:23 +0200 | [diff] [blame] | 500 | return _lpuart_serial_init(dev); |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 501 | } |
Alison Wang | e283053 | 2013-05-27 22:55:45 +0000 | [diff] [blame] | 502 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 503 | static int lpuart_serial_of_to_plat(struct udevice *dev) |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 504 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 505 | struct lpuart_serial_plat *plat = dev_get_plat(dev); |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 506 | const void *blob = gd->fdt_blob; |
Simon Glass | 7a49443 | 2017-05-17 17:18:09 -0600 | [diff] [blame] | 507 | int node = dev_of_offset(dev); |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 508 | fdt_addr_t addr; |
| 509 | |
Masahiro Yamada | a89b4de | 2020-07-17 14:36:48 +0900 | [diff] [blame] | 510 | addr = dev_read_addr(dev); |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 511 | if (addr == FDT_ADDR_T_NONE) |
| 512 | return -EINVAL; |
| 513 | |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 514 | plat->reg = (void *)addr; |
| 515 | plat->flags = dev_get_driver_data(dev); |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 516 | |
Vabhav Sharma | a8f78c6 | 2019-01-31 12:08:10 +0000 | [diff] [blame] | 517 | if (fdtdec_get_bool(blob, node, "little-endian")) |
| 518 | plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG; |
| 519 | |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 520 | if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart")) |
| 521 | plat->devtype = DEV_LS1021A; |
| 522 | else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart")) |
| 523 | plat->devtype = DEV_MX7ULP; |
| 524 | else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart")) |
| 525 | plat->devtype = DEV_VF610; |
Peng Fan | b7f9ea9 | 2018-10-18 14:28:31 +0200 | [diff] [blame] | 526 | else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart")) |
| 527 | plat->devtype = DEV_IMX8; |
Giulio Benetti | 5eaa97e | 2020-01-10 15:51:43 +0100 | [diff] [blame] | 528 | else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart")) |
| 529 | plat->devtype = DEV_IMXRT; |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 530 | |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 531 | return 0; |
| 532 | } |
| 533 | |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 534 | static const struct dm_serial_ops lpuart_serial_ops = { |
| 535 | .putc = lpuart_serial_putc, |
| 536 | .pending = lpuart_serial_pending, |
| 537 | .getc = lpuart_serial_getc, |
| 538 | .setbrg = lpuart_serial_setbrg, |
| 539 | }; |
| 540 | |
| 541 | static const struct udevice_id lpuart_serial_ids[] = { |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 542 | { .compatible = "fsl,ls1021a-lpuart", .data = |
| 543 | LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG }, |
Michael Walle | b285de4 | 2021-10-13 18:14:19 +0200 | [diff] [blame] | 544 | { .compatible = "fsl,ls1028a-lpuart", |
| 545 | .data = LPUART_FLAG_REGMAP_32BIT_REG }, |
Peng Fan | dac2c94 | 2017-02-22 16:21:52 +0800 | [diff] [blame] | 546 | { .compatible = "fsl,imx7ulp-lpuart", |
| 547 | .data = LPUART_FLAG_REGMAP_32BIT_REG }, |
Peng Fan | 836a6cc | 2017-02-22 16:21:51 +0800 | [diff] [blame] | 548 | { .compatible = "fsl,vf610-lpuart"}, |
Peng Fan | b7f9ea9 | 2018-10-18 14:28:31 +0200 | [diff] [blame] | 549 | { .compatible = "fsl,imx8qm-lpuart", |
| 550 | .data = LPUART_FLAG_REGMAP_32BIT_REG }, |
Giulio Benetti | 5eaa97e | 2020-01-10 15:51:43 +0100 | [diff] [blame] | 551 | { .compatible = "fsl,imxrt-lpuart", |
| 552 | .data = LPUART_FLAG_REGMAP_32BIT_REG }, |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 553 | { } |
| 554 | }; |
| 555 | |
| 556 | U_BOOT_DRIVER(serial_lpuart) = { |
| 557 | .name = "serial_lpuart", |
| 558 | .id = UCLASS_SERIAL, |
| 559 | .of_match = lpuart_serial_ids, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 560 | .of_to_plat = lpuart_serial_of_to_plat, |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 561 | .plat_auto = sizeof(struct lpuart_serial_plat), |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 562 | .probe = lpuart_serial_probe, |
| 563 | .ops = &lpuart_serial_ops, |
Bin Meng | 8a70d6d | 2016-01-13 19:39:04 -0800 | [diff] [blame] | 564 | }; |