blob: 51e66abdbc15fd282e422886f987774e5332c620 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Alison Wange2830532013-05-27 22:55:45 +00002/*
Vabhav Sharmaa8f78c62019-01-31 12:08:10 +00003 * Copyright 2019 NXP
Alison Wange2830532013-05-27 22:55:45 +00004 * Copyright 2013 Freescale Semiconductor, Inc.
Alison Wange2830532013-05-27 22:55:45 +00005 */
6
7#include <common.h>
Tom Rini8c70baa2021-12-14 13:36:40 -05008#include <clock_legacy.h>
Peng Fan68e45632018-10-19 00:26:23 +02009#include <clk.h>
Bin Meng8a70d6d2016-01-13 19:39:04 -080010#include <dm.h>
Peng Fan836a6cc2017-02-22 16:21:51 +080011#include <fsl_lpuart.h>
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Alison Wange2830532013-05-27 22:55:45 +000013#include <watchdog.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060014#include <asm/global_data.h>
Alison Wange2830532013-05-27 22:55:45 +000015#include <asm/io.h>
16#include <serial.h>
Simon Glass9bc15642020-02-03 07:36:16 -070017#include <dm/device_compat.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060018#include <linux/bitops.h>
Alison Wange2830532013-05-27 22:55:45 +000019#include <linux/compiler.h>
20#include <asm/arch/imx-regs.h>
21#include <asm/arch/clock.h>
22
Bin Menga8cc1722016-01-13 19:39:01 -080023#define US1_TDRE (1 << 7)
24#define US1_RDRF (1 << 5)
25#define US1_OR (1 << 3)
26#define UC2_TE (1 << 3)
27#define UC2_RE (1 << 2)
28#define CFIFO_TXFLUSH (1 << 7)
29#define CFIFO_RXFLUSH (1 << 6)
30#define SFIFO_RXOF (1 << 2)
31#define SFIFO_RXUF (1 << 0)
Alison Wange2830532013-05-27 22:55:45 +000032
Jingchang Lu4a7154e2014-09-05 13:52:47 +080033#define STAT_LBKDIF (1 << 31)
34#define STAT_RXEDGIF (1 << 30)
35#define STAT_TDRE (1 << 23)
36#define STAT_RDRF (1 << 21)
37#define STAT_IDLE (1 << 20)
38#define STAT_OR (1 << 19)
39#define STAT_NF (1 << 18)
40#define STAT_FE (1 << 17)
41#define STAT_PF (1 << 16)
42#define STAT_MA1F (1 << 15)
43#define STAT_MA2F (1 << 14)
44#define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
Bin Menga8cc1722016-01-13 19:39:01 -080045 STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
Jingchang Lu4a7154e2014-09-05 13:52:47 +080046
47#define CTRL_TE (1 << 19)
48#define CTRL_RE (1 << 18)
49
Ye Lia2aedcb2018-10-18 14:28:32 +020050#define FIFO_RXFLUSH BIT(14)
51#define FIFO_TXFLUSH BIT(15)
52#define FIFO_TXSIZE_MASK 0x70
53#define FIFO_TXSIZE_OFF 4
54#define FIFO_RXSIZE_MASK 0x7
55#define FIFO_RXSIZE_OFF 0
Jingchang Lu4a7154e2014-09-05 13:52:47 +080056#define FIFO_TXFE 0x80
Giulio Benetti5eaa97e2020-01-10 15:51:43 +010057#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
Peng Fanb7f9ea92018-10-18 14:28:31 +020058#define FIFO_RXFE 0x08
59#else
Jingchang Lu4a7154e2014-09-05 13:52:47 +080060#define FIFO_RXFE 0x40
Peng Fanb7f9ea92018-10-18 14:28:31 +020061#endif
Jingchang Lu4a7154e2014-09-05 13:52:47 +080062
Ye Lia2aedcb2018-10-18 14:28:32 +020063#define WATER_TXWATER_OFF 0
Jingchang Lu4a7154e2014-09-05 13:52:47 +080064#define WATER_RXWATER_OFF 16
65
Alison Wange2830532013-05-27 22:55:45 +000066DECLARE_GLOBAL_DATA_PTR;
67
Peng Fan836a6cc2017-02-22 16:21:51 +080068#define LPUART_FLAG_REGMAP_32BIT_REG BIT(0)
69#define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1)
70
Peng Fandac2c942017-02-22 16:21:52 +080071enum lpuart_devtype {
72 DEV_VF610 = 1,
73 DEV_LS1021A,
Peng Fanb7f9ea92018-10-18 14:28:31 +020074 DEV_MX7ULP,
Giulio Benetti5eaa97e2020-01-10 15:51:43 +010075 DEV_IMX8,
76 DEV_IMXRT,
Peng Fandac2c942017-02-22 16:21:52 +080077};
78
Simon Glassb75b15b2020-12-03 16:55:23 -070079struct lpuart_serial_plat {
Peng Fan836a6cc2017-02-22 16:21:51 +080080 void *reg;
Peng Fandac2c942017-02-22 16:21:52 +080081 enum lpuart_devtype devtype;
Peng Fan836a6cc2017-02-22 16:21:51 +080082 ulong flags;
Bin Meng8a70d6d2016-01-13 19:39:04 -080083};
84
Peng Fan836a6cc2017-02-22 16:21:51 +080085static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
86{
87 if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
88 if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
89 *(u32 *)val = in_be32(addr);
90 else
91 *(u32 *)val = in_le32(addr);
92 }
93}
94
95static void lpuart_write32(u32 flags, u32 *addr, u32 val)
96{
97 if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
98 if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
99 out_be32(addr, val);
100 else
101 out_le32(addr, val);
102 }
103}
104
105
Peng Fan836a6cc2017-02-22 16:21:51 +0800106u32 __weak get_lpuart_clk(void)
Alison Wange2830532013-05-27 22:55:45 +0000107{
Tom Rini8c70baa2021-12-14 13:36:40 -0500108 return get_board_sys_clk();
Peng Fan836a6cc2017-02-22 16:21:51 +0800109}
110
Ye Li86cf6992019-07-11 03:33:34 +0000111#if CONFIG_IS_ENABLED(CLK)
Peng Fan68e45632018-10-19 00:26:23 +0200112static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
113{
114 struct clk per_clk;
115 ulong rate;
116 int ret;
117
118 ret = clk_get_by_name(dev, "per", &per_clk);
119 if (ret) {
120 dev_err(dev, "Failed to get per clk: %d\n", ret);
121 return ret;
122 }
123
124 rate = clk_get_rate(&per_clk);
125 if ((long)rate <= 0) {
126 dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
127 return ret;
128 }
129 *clk = rate;
130 return 0;
131}
132#else
133static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
134{ return -ENOSYS; }
135#endif
136
Peng Fan836a6cc2017-02-22 16:21:51 +0800137static bool is_lpuart32(struct udevice *dev)
138{
Simon Glass95588622020-12-22 19:30:28 -0700139 struct lpuart_serial_plat *plat = dev_get_plat(dev);
Peng Fan836a6cc2017-02-22 16:21:51 +0800140
141 return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
142}
143
Peng Fan68e45632018-10-19 00:26:23 +0200144static void _lpuart_serial_setbrg(struct udevice *dev,
Peng Fan836a6cc2017-02-22 16:21:51 +0800145 int baudrate)
146{
Simon Glassb75b15b2020-12-03 16:55:23 -0700147 struct lpuart_serial_plat *plat = dev_get_plat(dev);
Peng Fan836a6cc2017-02-22 16:21:51 +0800148 struct lpuart_fsl *base = plat->reg;
Peng Fan68e45632018-10-19 00:26:23 +0200149 u32 clk;
Alison Wange2830532013-05-27 22:55:45 +0000150 u16 sbr;
Peng Fan68e45632018-10-19 00:26:23 +0200151 int ret;
152
Ye Li86cf6992019-07-11 03:33:34 +0000153 if (CONFIG_IS_ENABLED(CLK)) {
Peng Fan68e45632018-10-19 00:26:23 +0200154 ret = get_lpuart_clk_rate(dev, &clk);
155 if (ret)
156 return;
157 } else {
158 clk = get_lpuart_clk();
159 }
Alison Wange2830532013-05-27 22:55:45 +0000160
Bin Meng6338fbd2016-01-13 19:39:03 -0800161 sbr = (u16)(clk / (16 * baudrate));
Alison Wange2830532013-05-27 22:55:45 +0000162
Bin Menga8cc1722016-01-13 19:39:01 -0800163 /* place adjustment later - n/32 BRFA */
Alison Wange2830532013-05-27 22:55:45 +0000164 __raw_writeb(sbr >> 8, &base->ubdh);
165 __raw_writeb(sbr & 0xff, &base->ubdl);
166}
167
Simon Glassb75b15b2020-12-03 16:55:23 -0700168static int _lpuart_serial_getc(struct lpuart_serial_plat *plat)
Alison Wange2830532013-05-27 22:55:45 +0000169{
Peng Fan836a6cc2017-02-22 16:21:51 +0800170 struct lpuart_fsl *base = plat->reg;
Pali Rohár241f12d2022-12-11 00:31:21 +0100171 if (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
172 return -EAGAIN;
Alison Wange2830532013-05-27 22:55:45 +0000173
Stefan Agner24482912014-08-19 17:54:27 +0200174 barrier();
Alison Wange2830532013-05-27 22:55:45 +0000175
176 return __raw_readb(&base->ud);
177}
178
Pali Rohár241f12d2022-12-11 00:31:21 +0100179static int _lpuart_serial_putc(struct lpuart_serial_plat *plat,
Peng Fan836a6cc2017-02-22 16:21:51 +0800180 const char c)
Alison Wange2830532013-05-27 22:55:45 +0000181{
Peng Fan836a6cc2017-02-22 16:21:51 +0800182 struct lpuart_fsl *base = plat->reg;
183
Pali Rohár241f12d2022-12-11 00:31:21 +0100184 if (!(__raw_readb(&base->us1) & US1_TDRE))
185 return -EAGAIN;
Alison Wange2830532013-05-27 22:55:45 +0000186
187 __raw_writeb(c, &base->ud);
Pali Rohár241f12d2022-12-11 00:31:21 +0100188 return 0;
Alison Wange2830532013-05-27 22:55:45 +0000189}
190
Bin Menga8cc1722016-01-13 19:39:01 -0800191/* Test whether a character is in the RX buffer */
Simon Glassb75b15b2020-12-03 16:55:23 -0700192static int _lpuart_serial_tstc(struct lpuart_serial_plat *plat)
Alison Wange2830532013-05-27 22:55:45 +0000193{
Peng Fan836a6cc2017-02-22 16:21:51 +0800194 struct lpuart_fsl *base = plat->reg;
195
Alison Wange2830532013-05-27 22:55:45 +0000196 if (__raw_readb(&base->urcfifo) == 0)
197 return 0;
198
199 return 1;
200}
201
202/*
203 * Initialise the serial port with the given baudrate. The settings
204 * are always 8 data bits, no parity, 1 stop bit, no start bits.
205 */
Peng Fan68e45632018-10-19 00:26:23 +0200206static int _lpuart_serial_init(struct udevice *dev)
Alison Wange2830532013-05-27 22:55:45 +0000207{
Simon Glassb75b15b2020-12-03 16:55:23 -0700208 struct lpuart_serial_plat *plat = dev_get_plat(dev);
Peng Fan836a6cc2017-02-22 16:21:51 +0800209 struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
Alison Wange2830532013-05-27 22:55:45 +0000210 u8 ctrl;
211
212 ctrl = __raw_readb(&base->uc2);
213 ctrl &= ~UC2_RE;
214 ctrl &= ~UC2_TE;
215 __raw_writeb(ctrl, &base->uc2);
216
217 __raw_writeb(0, &base->umodem);
218 __raw_writeb(0, &base->uc1);
219
Stefan Agner190f1d22014-08-19 17:54:28 +0200220 /* Disable FIFO and flush buffer */
221 __raw_writeb(0x0, &base->upfifo);
222 __raw_writeb(0x0, &base->utwfifo);
223 __raw_writeb(0x1, &base->urwfifo);
224 __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
225
Alison Wange2830532013-05-27 22:55:45 +0000226 /* provide data bits, parity, stop bit, etc */
Peng Fan68e45632018-10-19 00:26:23 +0200227 _lpuart_serial_setbrg(dev, gd->baudrate);
Alison Wange2830532013-05-27 22:55:45 +0000228
229 __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
230
231 return 0;
232}
233
Peng Fan68e45632018-10-19 00:26:23 +0200234static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
Peng Fandac2c942017-02-22 16:21:52 +0800235 int baudrate)
236{
Simon Glassb75b15b2020-12-03 16:55:23 -0700237 struct lpuart_serial_plat *plat = dev_get_plat(dev);
Peng Fandac2c942017-02-22 16:21:52 +0800238 struct lpuart_fsl_reg32 *base = plat->reg;
239 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
Peng Fan68e45632018-10-19 00:26:23 +0200240 u32 clk;
241 int ret;
242
Ye Li86cf6992019-07-11 03:33:34 +0000243 if (CONFIG_IS_ENABLED(CLK)) {
Peng Fan68e45632018-10-19 00:26:23 +0200244 ret = get_lpuart_clk_rate(dev, &clk);
245 if (ret)
246 return;
247 } else {
248 clk = get_lpuart_clk();
249 }
Peng Fandac2c942017-02-22 16:21:52 +0800250
251 baud_diff = baudrate;
252 osr = 0;
253 sbr = 0;
254
255 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
256 tmp_sbr = (clk / (baudrate * tmp_osr));
257
258 if (tmp_sbr == 0)
259 tmp_sbr = 1;
260
261 /*calculate difference in actual buad w/ current values */
262 tmp_diff = (clk / (tmp_osr * tmp_sbr));
263 tmp_diff = tmp_diff - baudrate;
264
265 /* select best values between sbr and sbr+1 */
266 if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
267 tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
268 tmp_sbr++;
269 }
270
271 if (tmp_diff <= baud_diff) {
272 baud_diff = tmp_diff;
273 osr = tmp_osr;
274 sbr = tmp_sbr;
275 }
276 }
277
278 /*
279 * TODO: handle buadrate outside acceptable rate
280 * if (baudDiff > ((config->baudRate_Bps / 100) * 3))
281 * {
282 * Unacceptable baud rate difference of more than 3%
283 * return kStatus_LPUART_BaudrateNotSupport;
284 * }
285 */
286 tmp = in_le32(&base->baud);
287
288 if ((osr > 3) && (osr < 8))
289 tmp |= LPUART_BAUD_BOTHEDGE_MASK;
290
291 tmp &= ~LPUART_BAUD_OSR_MASK;
292 tmp |= LPUART_BAUD_OSR(osr-1);
293
294 tmp &= ~LPUART_BAUD_SBR_MASK;
295 tmp |= LPUART_BAUD_SBR(sbr);
296
297 /* explicitly disable 10 bit mode & set 1 stop bit */
298 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
299
300 out_le32(&base->baud, tmp);
301}
302
Peng Fan68e45632018-10-19 00:26:23 +0200303static void _lpuart32_serial_setbrg(struct udevice *dev,
Peng Fan836a6cc2017-02-22 16:21:51 +0800304 int baudrate)
Bin Meng8a70d6d2016-01-13 19:39:04 -0800305{
Simon Glassb75b15b2020-12-03 16:55:23 -0700306 struct lpuart_serial_plat *plat = dev_get_plat(dev);
Peng Fan836a6cc2017-02-22 16:21:51 +0800307 struct lpuart_fsl_reg32 *base = plat->reg;
Peng Fan68e45632018-10-19 00:26:23 +0200308 u32 clk;
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800309 u32 sbr;
Peng Fan68e45632018-10-19 00:26:23 +0200310 int ret;
311
Ye Li86cf6992019-07-11 03:33:34 +0000312 if (CONFIG_IS_ENABLED(CLK)) {
Peng Fan68e45632018-10-19 00:26:23 +0200313 ret = get_lpuart_clk_rate(dev, &clk);
314 if (ret)
315 return;
316 } else {
317 clk = get_lpuart_clk();
318 }
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800319
Bin Meng6338fbd2016-01-13 19:39:03 -0800320 sbr = (clk / (16 * baudrate));
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800321
Bin Menga8cc1722016-01-13 19:39:01 -0800322 /* place adjustment later - n/32 BRFA */
Peng Fan836a6cc2017-02-22 16:21:51 +0800323 lpuart_write32(plat->flags, &base->baud, sbr);
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800324}
325
Simon Glassb75b15b2020-12-03 16:55:23 -0700326static int _lpuart32_serial_getc(struct lpuart_serial_plat *plat)
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800327{
Peng Fan836a6cc2017-02-22 16:21:51 +0800328 struct lpuart_fsl_reg32 *base = plat->reg;
Peng Fandac2c942017-02-22 16:21:52 +0800329 u32 stat, val;
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800330
Peng Fan836a6cc2017-02-22 16:21:51 +0800331 lpuart_read32(plat->flags, &base->stat, &stat);
Pali Rohár241f12d2022-12-11 00:31:21 +0100332 if ((stat & STAT_RDRF) == 0) {
Peng Fan836a6cc2017-02-22 16:21:51 +0800333 lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
Pali Rohár241f12d2022-12-11 00:31:21 +0100334 return -EAGAIN;
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800335 }
336
Peng Fandac2c942017-02-22 16:21:52 +0800337 lpuart_read32(plat->flags, &base->data, &val);
Peng Fan836a6cc2017-02-22 16:21:51 +0800338
Sriram Dash32cf46c2018-01-10 11:57:14 +0530339 lpuart_read32(plat->flags, &base->stat, &stat);
340 if (stat & STAT_OR)
341 lpuart_write32(plat->flags, &base->stat, STAT_OR);
Peng Fandac2c942017-02-22 16:21:52 +0800342
343 return val & 0x3ff;
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800344}
345
Pali Rohár241f12d2022-12-11 00:31:21 +0100346static int _lpuart32_serial_putc(struct lpuart_serial_plat *plat,
Peng Fan836a6cc2017-02-22 16:21:51 +0800347 const char c)
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800348{
Peng Fan836a6cc2017-02-22 16:21:51 +0800349 struct lpuart_fsl_reg32 *base = plat->reg;
350 u32 stat;
351
Pali Rohár241f12d2022-12-11 00:31:21 +0100352 lpuart_read32(plat->flags, &base->stat, &stat);
353 if (!(stat & STAT_TDRE))
354 return -EAGAIN;
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800355
Peng Fan836a6cc2017-02-22 16:21:51 +0800356 lpuart_write32(plat->flags, &base->data, c);
Pali Rohár241f12d2022-12-11 00:31:21 +0100357 return 0;
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800358}
359
Bin Menga8cc1722016-01-13 19:39:01 -0800360/* Test whether a character is in the RX buffer */
Simon Glassb75b15b2020-12-03 16:55:23 -0700361static int _lpuart32_serial_tstc(struct lpuart_serial_plat *plat)
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800362{
Peng Fan836a6cc2017-02-22 16:21:51 +0800363 struct lpuart_fsl_reg32 *base = plat->reg;
364 u32 water;
365
366 lpuart_read32(plat->flags, &base->water, &water);
367
368 if ((water >> 24) == 0)
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800369 return 0;
370
371 return 1;
372}
373
374/*
375 * Initialise the serial port with the given baudrate. The settings
376 * are always 8 data bits, no parity, 1 stop bit, no start bits.
377 */
Peng Fan68e45632018-10-19 00:26:23 +0200378static int _lpuart32_serial_init(struct udevice *dev)
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800379{
Simon Glassb75b15b2020-12-03 16:55:23 -0700380 struct lpuart_serial_plat *plat = dev_get_plat(dev);
Peng Fan836a6cc2017-02-22 16:21:51 +0800381 struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
Ye Lia2aedcb2018-10-18 14:28:32 +0200382 u32 val, tx_fifo_size;
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800383
Ye Lia2aedcb2018-10-18 14:28:32 +0200384 lpuart_read32(plat->flags, &base->ctrl, &val);
385 val &= ~CTRL_RE;
386 val &= ~CTRL_TE;
387 lpuart_write32(plat->flags, &base->ctrl, val);
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800388
Peng Fan836a6cc2017-02-22 16:21:51 +0800389 lpuart_write32(plat->flags, &base->modir, 0);
Ye Lia2aedcb2018-10-18 14:28:32 +0200390
391 lpuart_read32(plat->flags, &base->fifo, &val);
392 tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
393 /* Set the TX water to half of FIFO size */
394 if (tx_fifo_size > 1)
395 tx_fifo_size = tx_fifo_size >> 1;
396
397 /* Set RX water to 0, to be triggered by any receive data */
398 lpuart_write32(plat->flags, &base->water,
399 (tx_fifo_size << WATER_TXWATER_OFF));
400
401 /* Enable TX and RX FIFO */
402 val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
403 lpuart_write32(plat->flags, &base->fifo, val);
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800404
Peng Fan836a6cc2017-02-22 16:21:51 +0800405 lpuart_write32(plat->flags, &base->match, 0);
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800406
Giulio Benetti5eaa97e2020-01-10 15:51:43 +0100407 if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
408 plat->devtype == DEV_IMXRT) {
Peng Fan68e45632018-10-19 00:26:23 +0200409 _lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
Peng Fandac2c942017-02-22 16:21:52 +0800410 } else {
411 /* provide data bits, parity, stop bit, etc */
Peng Fan68e45632018-10-19 00:26:23 +0200412 _lpuart32_serial_setbrg(dev, gd->baudrate);
Peng Fandac2c942017-02-22 16:21:52 +0800413 }
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800414
Peng Fan836a6cc2017-02-22 16:21:51 +0800415 lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);
Jingchang Lu4a7154e2014-09-05 13:52:47 +0800416
417 return 0;
418}
419
Peng Fan836a6cc2017-02-22 16:21:51 +0800420static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
Bin Meng8a70d6d2016-01-13 19:39:04 -0800421{
Simon Glassb75b15b2020-12-03 16:55:23 -0700422 struct lpuart_serial_plat *plat = dev_get_plat(dev);
Bin Meng8a70d6d2016-01-13 19:39:04 -0800423
Peng Fandac2c942017-02-22 16:21:52 +0800424 if (is_lpuart32(dev)) {
Giulio Benetti5eaa97e2020-01-10 15:51:43 +0100425 if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
426 plat->devtype == DEV_IMXRT)
Peng Fan68e45632018-10-19 00:26:23 +0200427 _lpuart32_serial_setbrg_7ulp(dev, baudrate);
Peng Fandac2c942017-02-22 16:21:52 +0800428 else
Peng Fan68e45632018-10-19 00:26:23 +0200429 _lpuart32_serial_setbrg(dev, baudrate);
Peng Fandac2c942017-02-22 16:21:52 +0800430 } else {
Peng Fan68e45632018-10-19 00:26:23 +0200431 _lpuart_serial_setbrg(dev, baudrate);
Peng Fandac2c942017-02-22 16:21:52 +0800432 }
Bin Meng8a70d6d2016-01-13 19:39:04 -0800433
434 return 0;
435}
436
Peng Fan836a6cc2017-02-22 16:21:51 +0800437static int lpuart_serial_getc(struct udevice *dev)
Bin Meng8a70d6d2016-01-13 19:39:04 -0800438{
Simon Glass95588622020-12-22 19:30:28 -0700439 struct lpuart_serial_plat *plat = dev_get_plat(dev);
Bin Meng8a70d6d2016-01-13 19:39:04 -0800440
Peng Fan836a6cc2017-02-22 16:21:51 +0800441 if (is_lpuart32(dev))
442 return _lpuart32_serial_getc(plat);
443
444 return _lpuart_serial_getc(plat);
Bin Meng8a70d6d2016-01-13 19:39:04 -0800445}
446
Peng Fan836a6cc2017-02-22 16:21:51 +0800447static int lpuart_serial_putc(struct udevice *dev, const char c)
Bin Meng8a70d6d2016-01-13 19:39:04 -0800448{
Simon Glass95588622020-12-22 19:30:28 -0700449 struct lpuart_serial_plat *plat = dev_get_plat(dev);
Bin Meng8a70d6d2016-01-13 19:39:04 -0800450
Peng Fan836a6cc2017-02-22 16:21:51 +0800451 if (is_lpuart32(dev))
Pali Rohár241f12d2022-12-11 00:31:21 +0100452 return _lpuart32_serial_putc(plat, c);
Bin Meng8a70d6d2016-01-13 19:39:04 -0800453
Pali Rohár241f12d2022-12-11 00:31:21 +0100454 return _lpuart_serial_putc(plat, c);
Bin Meng8a70d6d2016-01-13 19:39:04 -0800455}
456
Peng Fan836a6cc2017-02-22 16:21:51 +0800457static int lpuart_serial_pending(struct udevice *dev, bool input)
Bin Meng8a70d6d2016-01-13 19:39:04 -0800458{
Simon Glass95588622020-12-22 19:30:28 -0700459 struct lpuart_serial_plat *plat = dev_get_plat(dev);
Bin Meng8a70d6d2016-01-13 19:39:04 -0800460 struct lpuart_fsl *reg = plat->reg;
Peng Fan836a6cc2017-02-22 16:21:51 +0800461 struct lpuart_fsl_reg32 *reg32 = plat->reg;
462 u32 stat;
463
464 if (is_lpuart32(dev)) {
465 if (input) {
466 return _lpuart32_serial_tstc(plat);
467 } else {
468 lpuart_read32(plat->flags, &reg32->stat, &stat);
469 return stat & STAT_TDRE ? 0 : 1;
470 }
471 }
Bin Meng8a70d6d2016-01-13 19:39:04 -0800472
473 if (input)
Peng Fan836a6cc2017-02-22 16:21:51 +0800474 return _lpuart_serial_tstc(plat);
Bin Meng8a70d6d2016-01-13 19:39:04 -0800475 else
Peng Fan836a6cc2017-02-22 16:21:51 +0800476 return __raw_readb(&reg->us1) & US1_TDRE ? 0 : 1;
Bin Meng8a70d6d2016-01-13 19:39:04 -0800477}
478
Peng Fan836a6cc2017-02-22 16:21:51 +0800479static int lpuart_serial_probe(struct udevice *dev)
Bin Meng8a70d6d2016-01-13 19:39:04 -0800480{
Giulio Benetti0ad8b9c2020-01-10 15:47:05 +0100481#if CONFIG_IS_ENABLED(CLK)
482 struct clk per_clk;
483 int ret;
484
485 ret = clk_get_by_name(dev, "per", &per_clk);
486 if (!ret) {
487 ret = clk_enable(&per_clk);
488 if (ret) {
489 dev_err(dev, "Failed to get per clk: %d\n", ret);
490 return ret;
491 }
492 } else {
Giulio Benetti8bb8dcf2020-01-31 14:39:47 +0100493 debug("%s: Failed to get per clk: %d\n", __func__, ret);
Giulio Benetti0ad8b9c2020-01-10 15:47:05 +0100494 }
495#endif
496
Peng Fan836a6cc2017-02-22 16:21:51 +0800497 if (is_lpuart32(dev))
Peng Fan68e45632018-10-19 00:26:23 +0200498 return _lpuart32_serial_init(dev);
Peng Fan836a6cc2017-02-22 16:21:51 +0800499 else
Peng Fan68e45632018-10-19 00:26:23 +0200500 return _lpuart_serial_init(dev);
Bin Meng8a70d6d2016-01-13 19:39:04 -0800501}
Alison Wange2830532013-05-27 22:55:45 +0000502
Simon Glassaad29ae2020-12-03 16:55:21 -0700503static int lpuart_serial_of_to_plat(struct udevice *dev)
Bin Meng8a70d6d2016-01-13 19:39:04 -0800504{
Simon Glass95588622020-12-22 19:30:28 -0700505 struct lpuart_serial_plat *plat = dev_get_plat(dev);
Peng Fandac2c942017-02-22 16:21:52 +0800506 const void *blob = gd->fdt_blob;
Simon Glass7a494432017-05-17 17:18:09 -0600507 int node = dev_of_offset(dev);
Bin Meng8a70d6d2016-01-13 19:39:04 -0800508 fdt_addr_t addr;
509
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +0900510 addr = dev_read_addr(dev);
Bin Meng8a70d6d2016-01-13 19:39:04 -0800511 if (addr == FDT_ADDR_T_NONE)
512 return -EINVAL;
513
Peng Fan836a6cc2017-02-22 16:21:51 +0800514 plat->reg = (void *)addr;
515 plat->flags = dev_get_driver_data(dev);
Bin Meng8a70d6d2016-01-13 19:39:04 -0800516
Vabhav Sharmaa8f78c62019-01-31 12:08:10 +0000517 if (fdtdec_get_bool(blob, node, "little-endian"))
518 plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;
519
Peng Fandac2c942017-02-22 16:21:52 +0800520 if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
521 plat->devtype = DEV_LS1021A;
522 else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
523 plat->devtype = DEV_MX7ULP;
524 else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
525 plat->devtype = DEV_VF610;
Peng Fanb7f9ea92018-10-18 14:28:31 +0200526 else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
527 plat->devtype = DEV_IMX8;
Giulio Benetti5eaa97e2020-01-10 15:51:43 +0100528 else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
529 plat->devtype = DEV_IMXRT;
Peng Fandac2c942017-02-22 16:21:52 +0800530
Bin Meng8a70d6d2016-01-13 19:39:04 -0800531 return 0;
532}
533
Bin Meng8a70d6d2016-01-13 19:39:04 -0800534static const struct dm_serial_ops lpuart_serial_ops = {
535 .putc = lpuart_serial_putc,
536 .pending = lpuart_serial_pending,
537 .getc = lpuart_serial_getc,
538 .setbrg = lpuart_serial_setbrg,
539};
540
541static const struct udevice_id lpuart_serial_ids[] = {
Peng Fan836a6cc2017-02-22 16:21:51 +0800542 { .compatible = "fsl,ls1021a-lpuart", .data =
543 LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
Michael Walleb285de42021-10-13 18:14:19 +0200544 { .compatible = "fsl,ls1028a-lpuart",
545 .data = LPUART_FLAG_REGMAP_32BIT_REG },
Peng Fandac2c942017-02-22 16:21:52 +0800546 { .compatible = "fsl,imx7ulp-lpuart",
547 .data = LPUART_FLAG_REGMAP_32BIT_REG },
Peng Fan836a6cc2017-02-22 16:21:51 +0800548 { .compatible = "fsl,vf610-lpuart"},
Peng Fanb7f9ea92018-10-18 14:28:31 +0200549 { .compatible = "fsl,imx8qm-lpuart",
550 .data = LPUART_FLAG_REGMAP_32BIT_REG },
Giulio Benetti5eaa97e2020-01-10 15:51:43 +0100551 { .compatible = "fsl,imxrt-lpuart",
552 .data = LPUART_FLAG_REGMAP_32BIT_REG },
Bin Meng8a70d6d2016-01-13 19:39:04 -0800553 { }
554};
555
556U_BOOT_DRIVER(serial_lpuart) = {
557 .name = "serial_lpuart",
558 .id = UCLASS_SERIAL,
559 .of_match = lpuart_serial_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700560 .of_to_plat = lpuart_serial_of_to_plat,
Simon Glassb75b15b2020-12-03 16:55:23 -0700561 .plat_auto = sizeof(struct lpuart_serial_plat),
Bin Meng8a70d6d2016-01-13 19:39:04 -0800562 .probe = lpuart_serial_probe,
563 .ops = &lpuart_serial_ops,
Bin Meng8a70d6d2016-01-13 19:39:04 -0800564};