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Jagan Tekid69bf0b2018-08-05 14:31:54 +05301// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -050011#include <clk/sunxi.h>
Jagan Tekid69bf0b2018-08-05 14:31:54 +053012#include <dt-bindings/clock/sun8i-v3s-ccu.h>
13#include <dt-bindings/reset/sun8i-v3s-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060014#include <linux/bitops.h>
Jagan Tekid69bf0b2018-08-05 14:31:54 +053015
16static struct ccu_clk_gate v3s_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +000017 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Tekibc123132019-02-27 20:02:06 +053020 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
Jagan Tekid69bf0b2018-08-05 14:31:54 +053021 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
22
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -050023 [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
24 [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
Jagan Teki8cf08ea2018-12-30 21:29:24 +053025 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
26 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
27 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
28
Jagan Tekibc123132019-02-27 20:02:06 +053029 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
30
Jagan Tekid69bf0b2018-08-05 14:31:54 +053031 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
32};
33
34static struct ccu_reset v3s_resets[] = {
35 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
36
Andre Przywaraddf33c12019-01-29 15:54:09 +000037 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
38 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
39 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Tekibc123132019-02-27 20:02:06 +053040 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
Jagan Tekid69bf0b2018-08-05 14:31:54 +053041 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
Jagan Tekib490aa52018-12-30 21:37:31 +053042
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -050043 [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
44 [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
Jagan Tekib490aa52018-12-30 21:37:31 +053045 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
46 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
47 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
Jagan Tekid69bf0b2018-08-05 14:31:54 +053048};
49
50static const struct ccu_desc v3s_ccu_desc = {
51 .gates = v3s_gates,
52 .resets = v3s_resets,
53};
54
55static int v3s_clk_bind(struct udevice *dev)
56{
57 return sunxi_reset_bind(dev, ARRAY_SIZE(v3s_resets));
58}
59
60static const struct udevice_id v3s_clk_ids[] = {
61 { .compatible = "allwinner,sun8i-v3s-ccu",
62 .data = (ulong)&v3s_ccu_desc },
Icenowy Zheng18e4ab62020-10-26 22:18:02 +080063 { .compatible = "allwinner,sun8i-v3-ccu",
64 .data = (ulong)&v3s_ccu_desc },
Jagan Tekid69bf0b2018-08-05 14:31:54 +053065 { }
66};
67
68U_BOOT_DRIVER(clk_sun8i_v3s) = {
69 .name = "sun8i_v3s_ccu",
70 .id = UCLASS_CLK,
71 .of_match = v3s_clk_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -070072 .priv_auto = sizeof(struct ccu_priv),
Jagan Tekid69bf0b2018-08-05 14:31:54 +053073 .ops = &sunxi_clk_ops,
74 .probe = sunxi_clk_probe,
75 .bind = v3s_clk_bind,
76};