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Alex Marginean72f3aa52021-01-27 13:00:00 +02001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP LS1028A-QDS device tree fragment for RCW x5xx
4 *
Vladimir Oltean5041e422021-09-17 14:27:13 +03005 * Copyright 2019-2021 NXP
Alex Marginean72f3aa52021-01-27 13:00:00 +02006 */
7
8/*
9 * This setup is using SCH-28021 cards with VSC8514 QSGMII PHY in slot 2.
10 * This is only available on LS1028A QDS boards with lane B rework.
11 */
12&slot2 {
13 #include "fsl-sch-28021.dtsi"
14};
15
Michael Walle2a20ed12021-10-13 18:14:15 +020016&enetc_port2 {
Vladimir Olteanc32039a2021-06-29 20:53:11 +030017 status = "okay";
18};
19
Alex Marginean72f3aa52021-01-27 13:00:00 +020020&mscc_felix {
21 status = "okay";
22};
23
24&mscc_felix_port0 {
25 status = "okay";
26 phy-mode = "qsgmii";
Michael Walle2da16cd2021-10-13 18:14:05 +020027 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
Alex Marginean72f3aa52021-01-27 13:00:00 +020028};
29
30&mscc_felix_port1 {
31 status = "okay";
32 phy-mode = "qsgmii";
Michael Walle2da16cd2021-10-13 18:14:05 +020033 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
Alex Marginean72f3aa52021-01-27 13:00:00 +020034};
35
36&mscc_felix_port2 {
37 status = "okay";
38 phy-mode = "qsgmii";
Michael Walle2da16cd2021-10-13 18:14:05 +020039 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
Alex Marginean72f3aa52021-01-27 13:00:00 +020040};
41
42&mscc_felix_port3 {
43 status = "okay";
44 phy-mode = "qsgmii";
Michael Walle2da16cd2021-10-13 18:14:05 +020045 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
Alex Marginean72f3aa52021-01-27 13:00:00 +020046};
Vladimir Olteanc32039a2021-06-29 20:53:11 +030047
48&mscc_felix_port4 {
Michael Walle2a20ed12021-10-13 18:14:15 +020049 ethernet = <&enetc_port2>;
Vladimir Olteanc32039a2021-06-29 20:53:11 +030050 status = "okay";
51};