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git01.mediatek.com / filogic / uboot / b50abe2b1fefafb043cb1ce4f11e2a3b9f7ee7b3 / . / arch / arm / dts / am33xx.dtsi
blob: 42345375e684088187ebe2569125a27df1530e0a [file] [log] [blame]
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/pinctrl/am33xx.h>
13
14#include "skeleton.dtsi"
15
16/ {
17 compatible = "ti,am33xx";
18 interrupt-parent = <&intc>;
19
20 aliases {
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]38 };
39
40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 cpu@0 {
44 compatible = "arm,cortex-a8";
45 device_type = "cpu";
46 reg = <0>;
47
48 /*
49 * To consider voltage drop between PMIC and SoC,
50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]61
62 clocks = <&dpll_mpu_ck>;
63 clock-names = "cpu";
64
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]65 clock-latency = <300000>; /* From omap-cpufreq driver */
66 };
67 };
68
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]69 pmu {
70 compatible = "arm,cortex-a8-pmu";
71 interrupts = <3>;
72 };
73
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]74 /*
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]75 * The soc node represents the soc top level view. It is used for IPs
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]76 * that are not memory mapped in the MPU view or for the MPU itself.
77 */
78 soc {
79 compatible = "ti,omap-infra";
80 mpu {
81 compatible = "ti,omap3-mpu";
82 ti,hwmods = "mpu";
83 };
84 };
85
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]86 /*
87 * XXX: Use a flat representation of the AM33XX interconnect.
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]88 * The real AM33XX interconnect network is quite complex. Since
89 * it will not bring real advantage to represent that in DT
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]90 * for the moment, just use a fake OCP bus entry to represent
91 * the whole bus hierarchy.
92 */
93 ocp {
Hannes Schmelzer1ef0b902018-07-06 15:41:27 +0200[diff] [blame]94 u-boot,dm-spl;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]95 compatible = "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges;
99 ti,hwmods = "l3_main";
100
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]101 l4_wkup: l4_wkup@44c00000 {
102 compatible = "ti,am3-l4-wkup", "simple-bus";
103 #address-cells = <1>;
104 #size-cells = <1>;
105 ranges = <0 0x44c00000 0x280000>;
106
107 prcm: prcm@200000 {
108 compatible = "ti,am3-prcm";
109 reg = <0x200000 0x4000>;
110
111 prcm_clocks: clocks {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 };
115
116 prcm_clockdomains: clockdomains {
117 };
118 };
119
120 scm: scm@210000 {
121 compatible = "ti,am3-scm", "simple-bus";
122 reg = <0x210000 0x2000>;
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges = <0 0x210000 0x2000>;
126
127 am33xx_pinmux: pinmux@800 {
128 compatible = "pinctrl-single";
129 reg = <0x800 0x238>;
130 #address-cells = <1>;
131 #size-cells = <0>;
132 pinctrl-single,register-width = <32>;
133 pinctrl-single,function-mask = <0x7f>;
134 };
135
136 scm_conf: scm_conf@0 {
137 compatible = "syscon";
138 reg = <0x0 0x800>;
139 #address-cells = <1>;
140 #size-cells = <1>;
141
142 scm_clocks: clocks {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 };
146 };
147
148 scm_clockdomains: clockdomains {
149 };
150 };
151 };
152
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]153 intc: interrupt-controller@48200000 {
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]154 compatible = "ti,am33xx-intc";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]155 interrupt-controller;
156 #interrupt-cells = <1>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]157 reg = <0x48200000 0x1000>;
158 };
159
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]160 edma: edma@49000000 {
161 compatible = "ti,edma3";
162 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
163 reg = <0x49000000 0x10000>,
164 <0x44e10f90 0x40>;
165 interrupts = <12 13 14>;
166 #dma-cells = <1>;
167 };
168
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]169 gpio0: gpio@44e07000 {
170 compatible = "ti,omap4-gpio";
171 ti,hwmods = "gpio1";
172 gpio-controller;
173 #gpio-cells = <2>;
174 interrupt-controller;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]175 #interrupt-cells = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]176 reg = <0x44e07000 0x1000>;
177 interrupts = <96>;
178 };
179
180 gpio1: gpio@4804c000 {
181 compatible = "ti,omap4-gpio";
182 ti,hwmods = "gpio2";
183 gpio-controller;
184 #gpio-cells = <2>;
185 interrupt-controller;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]186 #interrupt-cells = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]187 reg = <0x4804c000 0x1000>;
188 interrupts = <98>;
189 };
190
191 gpio2: gpio@481ac000 {
192 compatible = "ti,omap4-gpio";
193 ti,hwmods = "gpio3";
194 gpio-controller;
195 #gpio-cells = <2>;
196 interrupt-controller;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]197 #interrupt-cells = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]198 reg = <0x481ac000 0x1000>;
199 interrupts = <32>;
200 };
201
202 gpio3: gpio@481ae000 {
203 compatible = "ti,omap4-gpio";
204 ti,hwmods = "gpio4";
205 gpio-controller;
206 #gpio-cells = <2>;
207 interrupt-controller;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]208 #interrupt-cells = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]209 reg = <0x481ae000 0x1000>;
210 interrupts = <62>;
211 };
212
213 uart0: serial@44e09000 {
214 compatible = "ti,omap3-uart";
215 ti,hwmods = "uart1";
216 clock-frequency = <48000000>;
217 reg = <0x44e09000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]218 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]219 interrupts = <72>;
220 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]221 dmas = <&edma 26>, <&edma 27>;
222 dma-names = "tx", "rx";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]223 };
224
225 uart1: serial@48022000 {
226 compatible = "ti,omap3-uart";
227 ti,hwmods = "uart2";
228 clock-frequency = <48000000>;
229 reg = <0x48022000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]230 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]231 interrupts = <73>;
232 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]233 dmas = <&edma 28>, <&edma 29>;
234 dma-names = "tx", "rx";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]235 };
236
237 uart2: serial@48024000 {
238 compatible = "ti,omap3-uart";
239 ti,hwmods = "uart3";
240 clock-frequency = <48000000>;
241 reg = <0x48024000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]242 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]243 interrupts = <74>;
244 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]245 dmas = <&edma 30>, <&edma 31>;
246 dma-names = "tx", "rx";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]247 };
248
249 uart3: serial@481a6000 {
250 compatible = "ti,omap3-uart";
251 ti,hwmods = "uart4";
252 clock-frequency = <48000000>;
253 reg = <0x481a6000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]254 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]255 interrupts = <44>;
256 status = "disabled";
257 };
258
259 uart4: serial@481a8000 {
260 compatible = "ti,omap3-uart";
261 ti,hwmods = "uart5";
262 clock-frequency = <48000000>;
263 reg = <0x481a8000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]264 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]265 interrupts = <45>;
266 status = "disabled";
267 };
268
269 uart5: serial@481aa000 {
270 compatible = "ti,omap3-uart";
271 ti,hwmods = "uart6";
272 clock-frequency = <48000000>;
273 reg = <0x481aa000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]274 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]275 interrupts = <46>;
276 status = "disabled";
277 };
278
279 i2c0: i2c@44e0b000 {
280 compatible = "ti,omap4-i2c";
281 #address-cells = <1>;
282 #size-cells = <0>;
283 ti,hwmods = "i2c1";
284 reg = <0x44e0b000 0x1000>;
285 interrupts = <70>;
286 status = "disabled";
287 };
288
289 i2c1: i2c@4802a000 {
290 compatible = "ti,omap4-i2c";
291 #address-cells = <1>;
292 #size-cells = <0>;
293 ti,hwmods = "i2c2";
294 reg = <0x4802a000 0x1000>;
295 interrupts = <71>;
296 status = "disabled";
297 };
298
299 i2c2: i2c@4819c000 {
300 compatible = "ti,omap4-i2c";
301 #address-cells = <1>;
302 #size-cells = <0>;
303 ti,hwmods = "i2c3";
304 reg = <0x4819c000 0x1000>;
305 interrupts = <30>;
306 status = "disabled";
307 };
308
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]309 mmc1: mmc@48060000 {
310 compatible = "ti,omap4-hsmmc";
311 ti,hwmods = "mmc1";
312 ti,dual-volt;
313 ti,needs-special-reset;
314 ti,needs-special-hs-handling;
315 dmas = <&edma 24
316 &edma 25>;
317 dma-names = "tx", "rx";
318 interrupts = <64>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]319 reg = <0x48060000 0x1000>;
320 status = "disabled";
321 };
322
323 mmc2: mmc@481d8000 {
324 compatible = "ti,omap4-hsmmc";
325 ti,hwmods = "mmc2";
326 ti,needs-special-reset;
327 dmas = <&edma 2
328 &edma 3>;
329 dma-names = "tx", "rx";
330 interrupts = <28>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]331 reg = <0x481d8000 0x1000>;
332 status = "disabled";
333 };
334
335 mmc3: mmc@47810000 {
336 compatible = "ti,omap4-hsmmc";
337 ti,hwmods = "mmc3";
338 ti,needs-special-reset;
339 interrupts = <29>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]340 reg = <0x47810000 0x1000>;
341 status = "disabled";
342 };
343
344 hwspinlock: spinlock@480ca000 {
345 compatible = "ti,omap4-hwspinlock";
346 reg = <0x480ca000 0x1000>;
347 ti,hwmods = "spinlock";
348 #hwlock-cells = <1>;
349 };
350
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]351 wdt2: wdt@44e35000 {
352 compatible = "ti,omap3-wdt";
353 ti,hwmods = "wd_timer2";
354 reg = <0x44e35000 0x1000>;
355 interrupts = <91>;
356 };
357
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]358 dcan0: can@481cc000 {
359 compatible = "ti,am3352-d_can";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]360 ti,hwmods = "d_can0";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]361 reg = <0x481cc000 0x2000>;
362 clocks = <&dcan0_fck>;
363 clock-names = "fck";
364 syscon-raminit = <&scm_conf 0x644 0>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]365 interrupts = <52>;
366 status = "disabled";
367 };
368
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]369 dcan1: can@481d0000 {
370 compatible = "ti,am3352-d_can";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]371 ti,hwmods = "d_can1";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]372 reg = <0x481d0000 0x2000>;
373 clocks = <&dcan1_fck>;
374 clock-names = "fck";
375 syscon-raminit = <&scm_conf 0x644 1>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]376 interrupts = <55>;
377 status = "disabled";
378 };
379
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]380 mailbox: mailbox@480C8000 {
381 compatible = "ti,omap4-mailbox";
382 reg = <0x480C8000 0x200>;
383 interrupts = <77>;
384 ti,hwmods = "mailbox";
385 #mbox-cells = <1>;
386 ti,mbox-num-users = <4>;
387 ti,mbox-num-fifos = <8>;
388 mbox_wkupm3: wkup_m3 {
389 ti,mbox-tx = <0 0 0>;
390 ti,mbox-rx = <0 0 3>;
391 };
392 };
393
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]394 timer1: timer@44e31000 {
395 compatible = "ti,am335x-timer-1ms";
396 reg = <0x44e31000 0x400>;
397 interrupts = <67>;
398 ti,hwmods = "timer1";
399 ti,timer-alwon;
400 };
401
402 timer2: timer@48040000 {
403 compatible = "ti,am335x-timer";
404 reg = <0x48040000 0x400>;
405 interrupts = <68>;
406 ti,hwmods = "timer2";
407 };
408
409 timer3: timer@48042000 {
410 compatible = "ti,am335x-timer";
411 reg = <0x48042000 0x400>;
412 interrupts = <69>;
413 ti,hwmods = "timer3";
414 };
415
416 timer4: timer@48044000 {
417 compatible = "ti,am335x-timer";
418 reg = <0x48044000 0x400>;
419 interrupts = <92>;
420 ti,hwmods = "timer4";
421 ti,timer-pwm;
422 };
423
424 timer5: timer@48046000 {
425 compatible = "ti,am335x-timer";
426 reg = <0x48046000 0x400>;
427 interrupts = <93>;
428 ti,hwmods = "timer5";
429 ti,timer-pwm;
430 };
431
432 timer6: timer@48048000 {
433 compatible = "ti,am335x-timer";
434 reg = <0x48048000 0x400>;
435 interrupts = <94>;
436 ti,hwmods = "timer6";
437 ti,timer-pwm;
438 };
439
440 timer7: timer@4804a000 {
441 compatible = "ti,am335x-timer";
442 reg = <0x4804a000 0x400>;
443 interrupts = <95>;
444 ti,hwmods = "timer7";
445 ti,timer-pwm;
446 };
447
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]448 rtc: rtc@44e3e000 {
449 compatible = "ti,am3352-rtc", "ti,da830-rtc";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]450 reg = <0x44e3e000 0x1000>;
451 interrupts = <75
452 76>;
453 ti,hwmods = "rtc";
454 };
455
456 spi0: spi@48030000 {
457 compatible = "ti,omap4-mcspi";
458 #address-cells = <1>;
459 #size-cells = <0>;
460 reg = <0x48030000 0x400>;
461 interrupts = <65>;
462 ti,spi-num-cs = <2>;
463 ti,hwmods = "spi0";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]464 dmas = <&edma 16
465 &edma 17
466 &edma 18
467 &edma 19>;
468 dma-names = "tx0", "rx0", "tx1", "rx1";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]469 status = "disabled";
470 };
471
472 spi1: spi@481a0000 {
473 compatible = "ti,omap4-mcspi";
474 #address-cells = <1>;
475 #size-cells = <0>;
476 reg = <0x481a0000 0x400>;
477 interrupts = <125>;
478 ti,spi-num-cs = <2>;
479 ti,hwmods = "spi1";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]480 dmas = <&edma 42
481 &edma 43
482 &edma 44
483 &edma 45>;
484 dma-names = "tx0", "rx0", "tx1", "rx1";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]485 status = "disabled";
486 };
487
488 usb: usb@47400000 {
489 compatible = "ti,am33xx-usb";
490 reg = <0x47400000 0x1000>;
491 ranges;
492 #address-cells = <1>;
493 #size-cells = <1>;
494 ti,hwmods = "usb_otg_hs";
495 status = "disabled";
496
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]497 usb_ctrl_mod: control@44e10620 {
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]498 compatible = "ti,am335x-usb-ctrl-module";
499 reg = <0x44e10620 0x10
500 0x44e10648 0x4>;
501 reg-names = "phy_ctrl", "wakeup";
502 status = "disabled";
503 };
504
505 usb0_phy: usb-phy@47401300 {
506 compatible = "ti,am335x-usb-phy";
507 reg = <0x47401300 0x100>;
508 reg-names = "phy";
509 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]510 ti,ctrl_mod = <&usb_ctrl_mod>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]511 };
512
513 usb0: usb@47401000 {
514 compatible = "ti,musb-am33xx";
515 status = "disabled";
516 reg = <0x47401400 0x400
517 0x47401000 0x200>;
518 reg-names = "mc", "control";
519
520 interrupts = <18>;
521 interrupt-names = "mc";
522 dr_mode = "otg";
523 mentor,multipoint = <1>;
524 mentor,num-eps = <16>;
525 mentor,ram-bits = <12>;
526 mentor,power = <500>;
527 phys = <&usb0_phy>;
528
529 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
530 &cppi41dma 2 0 &cppi41dma 3 0
531 &cppi41dma 4 0 &cppi41dma 5 0
532 &cppi41dma 6 0 &cppi41dma 7 0
533 &cppi41dma 8 0 &cppi41dma 9 0
534 &cppi41dma 10 0 &cppi41dma 11 0
535 &cppi41dma 12 0 &cppi41dma 13 0
536 &cppi41dma 14 0 &cppi41dma 0 1
537 &cppi41dma 1 1 &cppi41dma 2 1
538 &cppi41dma 3 1 &cppi41dma 4 1
539 &cppi41dma 5 1 &cppi41dma 6 1
540 &cppi41dma 7 1 &cppi41dma 8 1
541 &cppi41dma 9 1 &cppi41dma 10 1
542 &cppi41dma 11 1 &cppi41dma 12 1
543 &cppi41dma 13 1 &cppi41dma 14 1>;
544 dma-names =
545 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
546 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
547 "rx14", "rx15",
548 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
549 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
550 "tx14", "tx15";
551 };
552
553 usb1_phy: usb-phy@47401b00 {
554 compatible = "ti,am335x-usb-phy";
555 reg = <0x47401b00 0x100>;
556 reg-names = "phy";
557 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]558 ti,ctrl_mod = <&usb_ctrl_mod>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]559 };
560
561 usb1: usb@47401800 {
562 compatible = "ti,musb-am33xx";
563 status = "disabled";
564 reg = <0x47401c00 0x400
565 0x47401800 0x200>;
566 reg-names = "mc", "control";
567 interrupts = <19>;
568 interrupt-names = "mc";
569 dr_mode = "otg";
570 mentor,multipoint = <1>;
571 mentor,num-eps = <16>;
572 mentor,ram-bits = <12>;
573 mentor,power = <500>;
574 phys = <&usb1_phy>;
575
576 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
577 &cppi41dma 17 0 &cppi41dma 18 0
578 &cppi41dma 19 0 &cppi41dma 20 0
579 &cppi41dma 21 0 &cppi41dma 22 0
580 &cppi41dma 23 0 &cppi41dma 24 0
581 &cppi41dma 25 0 &cppi41dma 26 0
582 &cppi41dma 27 0 &cppi41dma 28 0
583 &cppi41dma 29 0 &cppi41dma 15 1
584 &cppi41dma 16 1 &cppi41dma 17 1
585 &cppi41dma 18 1 &cppi41dma 19 1
586 &cppi41dma 20 1 &cppi41dma 21 1
587 &cppi41dma 22 1 &cppi41dma 23 1
588 &cppi41dma 24 1 &cppi41dma 25 1
589 &cppi41dma 26 1 &cppi41dma 27 1
590 &cppi41dma 28 1 &cppi41dma 29 1>;
591 dma-names =
592 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
593 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
594 "rx14", "rx15",
595 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
596 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
597 "tx14", "tx15";
598 };
599
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]600 cppi41dma: dma-controller@47402000 {
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]601 compatible = "ti,am3359-cppi41";
602 reg = <0x47400000 0x1000
603 0x47402000 0x1000
604 0x47403000 0x1000
605 0x47404000 0x4000>;
606 reg-names = "glue", "controller", "scheduler", "queuemgr";
607 interrupts = <17>;
608 interrupt-names = "glue";
609 #dma-cells = <2>;
610 #dma-channels = <30>;
611 #dma-requests = <256>;
612 status = "disabled";
613 };
614 };
615
616 epwmss0: epwmss@48300000 {
617 compatible = "ti,am33xx-pwmss";
618 reg = <0x48300000 0x10>;
619 ti,hwmods = "epwmss0";
620 #address-cells = <1>;
621 #size-cells = <1>;
622 status = "disabled";
623 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
624 0x48300180 0x48300180 0x80 /* EQEP */
625 0x48300200 0x48300200 0x80>; /* EHRPWM */
626
627 ecap0: ecap@48300100 {
628 compatible = "ti,am33xx-ecap";
629 #pwm-cells = <3>;
630 reg = <0x48300100 0x80>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]631 interrupts = <31>;
632 interrupt-names = "ecap0";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]633 ti,hwmods = "ecap0";
634 status = "disabled";
635 };
636
637 ehrpwm0: ehrpwm@48300200 {
638 compatible = "ti,am33xx-ehrpwm";
639 #pwm-cells = <3>;
640 reg = <0x48300200 0x80>;
641 ti,hwmods = "ehrpwm0";
642 status = "disabled";
643 };
644 };
645
646 epwmss1: epwmss@48302000 {
647 compatible = "ti,am33xx-pwmss";
648 reg = <0x48302000 0x10>;
649 ti,hwmods = "epwmss1";
650 #address-cells = <1>;
651 #size-cells = <1>;
652 status = "disabled";
653 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
654 0x48302180 0x48302180 0x80 /* EQEP */
655 0x48302200 0x48302200 0x80>; /* EHRPWM */
656
657 ecap1: ecap@48302100 {
658 compatible = "ti,am33xx-ecap";
659 #pwm-cells = <3>;
660 reg = <0x48302100 0x80>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]661 interrupts = <47>;
662 interrupt-names = "ecap1";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]663 ti,hwmods = "ecap1";
664 status = "disabled";
665 };
666
667 ehrpwm1: ehrpwm@48302200 {
668 compatible = "ti,am33xx-ehrpwm";
669 #pwm-cells = <3>;
670 reg = <0x48302200 0x80>;
671 ti,hwmods = "ehrpwm1";
672 status = "disabled";
673 };
674 };
675
676 epwmss2: epwmss@48304000 {
677 compatible = "ti,am33xx-pwmss";
678 reg = <0x48304000 0x10>;
679 ti,hwmods = "epwmss2";
680 #address-cells = <1>;
681 #size-cells = <1>;
682 status = "disabled";
683 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
684 0x48304180 0x48304180 0x80 /* EQEP */
685 0x48304200 0x48304200 0x80>; /* EHRPWM */
686
687 ecap2: ecap@48304100 {
688 compatible = "ti,am33xx-ecap";
689 #pwm-cells = <3>;
690 reg = <0x48304100 0x80>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]691 interrupts = <61>;
692 interrupt-names = "ecap2";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]693 ti,hwmods = "ecap2";
694 status = "disabled";
695 };
696
697 ehrpwm2: ehrpwm@48304200 {
698 compatible = "ti,am33xx-ehrpwm";
699 #pwm-cells = <3>;
700 reg = <0x48304200 0x80>;
701 ti,hwmods = "ehrpwm2";
702 status = "disabled";
703 };
704 };
705
706 mac: ethernet@4a100000 {
707 compatible = "ti,cpsw";
708 ti,hwmods = "cpgmac0";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]709 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
710 clock-names = "fck", "cpts";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]711 cpdma_channels = <8>;
712 ale_entries = <1024>;
713 bd_ram_size = <0x2000>;
714 no_bd_ram = <0>;
715 rx_descs = <64>;
716 mac_control = <0x20>;
717 slaves = <2>;
718 active_slave = <0>;
719 cpts_clock_mult = <0x80000000>;
720 cpts_clock_shift = <29>;
721 reg = <0x4a100000 0x800
722 0x4a101200 0x100>;
723 #address-cells = <1>;
724 #size-cells = <1>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]725 /*
726 * c0_rx_thresh_pend
727 * c0_rx_pend
728 * c0_tx_pend
729 * c0_misc_pend
730 */
731 interrupts = <40 41 42 43>;
732 ranges;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]733 syscon = <&scm_conf>;
734 status = "disabled";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]735
736 davinci_mdio: mdio@4a101000 {
737 compatible = "ti,davinci_mdio";
738 #address-cells = <1>;
739 #size-cells = <0>;
740 ti,hwmods = "davinci_mdio";
741 bus_freq = <1000000>;
742 reg = <0x4a101000 0x100>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]743 status = "disabled";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]744 };
745
746 cpsw_emac0: slave@4a100200 {
747 /* Filled in by U-Boot */
748 mac-address = [ 00 00 00 00 00 00 ];
749 };
750
751 cpsw_emac1: slave@4a100300 {
752 /* Filled in by U-Boot */
753 mac-address = [ 00 00 00 00 00 00 ];
754 };
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]755
756 phy_sel: cpsw-phy-sel@44e10650 {
757 compatible = "ti,am3352-cpsw-phy-sel";
758 reg= <0x44e10650 0x4>;
759 reg-names = "gmii-sel";
760 };
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]761 };
762
763 ocmcram: ocmcram@40300000 {
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]764 compatible = "mmio-sram";
765 reg = <0x40300000 0x10000>; /* 64k */
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]766 };
767
768 wkup_m3: wkup_m3@44d00000 {
769 compatible = "ti,am3353-wkup-m3";
770 reg = <0x44d00000 0x4000 /* M3 UMEM */
771 0x44d80000 0x2000>; /* M3 DMEM */
772 ti,hwmods = "wkup_m3";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]773 ti,no-reset-on-init;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]774 };
775
776 elm: elm@48080000 {
777 compatible = "ti,am3352-elm";
778 reg = <0x48080000 0x2000>;
779 interrupts = <4>;
780 ti,hwmods = "elm";
781 status = "disabled";
782 };
783
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]784 lcdc: lcdc@4830e000 {
785 compatible = "ti,am33xx-tilcdc";
786 reg = <0x4830e000 0x1000>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]787 interrupts = <36>;
788 ti,hwmods = "lcdc";
789 status = "disabled";
790 };
791
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]792 tscadc: tscadc@44e0d000 {
793 compatible = "ti,am3359-tscadc";
794 reg = <0x44e0d000 0x1000>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]795 interrupts = <16>;
796 ti,hwmods = "adc_tsc";
797 status = "disabled";
798
799 tsc {
800 compatible = "ti,am3359-tsc";
801 };
802 am335x_adc: adc {
803 #io-channel-cells = <1>;
804 compatible = "ti,am3359-adc";
805 };
806 };
807
808 gpmc: gpmc@50000000 {
809 compatible = "ti,am3352-gpmc";
810 ti,hwmods = "gpmc";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]811 ti,no-idle-on-init;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]812 reg = <0x50000000 0x2000>;
813 interrupts = <100>;
814 gpmc,num-cs = <7>;
815 gpmc,num-waitpins = <2>;
816 #address-cells = <2>;
817 #size-cells = <1>;
818 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]819 };
820
821 sham: sham@53100000 {
822 compatible = "ti,omap4-sham";
823 ti,hwmods = "sham";
824 reg = <0x53100000 0x200>;
825 interrupts = <109>;
826 dmas = <&edma 36>;
827 dma-names = "rx";
828 };
829
830 aes: aes@53500000 {
831 compatible = "ti,omap4-aes";
832 ti,hwmods = "aes";
833 reg = <0x53500000 0xa0>;
834 interrupts = <103>;
835 dmas = <&edma 6>,
836 <&edma 5>;
837 dma-names = "tx", "rx";
838 };
839
840 mcasp0: mcasp@48038000 {
841 compatible = "ti,am33xx-mcasp-audio";
842 ti,hwmods = "mcasp0";
843 reg = <0x48038000 0x2000>,
844 <0x46000000 0x400000>;
845 reg-names = "mpu", "dat";
846 interrupts = <80>, <81>;
847 interrupt-names = "tx", "rx";
848 status = "disabled";
849 dmas = <&edma 8>,
850 <&edma 9>;
851 dma-names = "tx", "rx";
852 };
853
854 mcasp1: mcasp@4803C000 {
855 compatible = "ti,am33xx-mcasp-audio";
856 ti,hwmods = "mcasp1";
857 reg = <0x4803C000 0x2000>,
858 <0x46400000 0x400000>;
859 reg-names = "mpu", "dat";
860 interrupts = <82>, <83>;
861 interrupt-names = "tx", "rx";
862 status = "disabled";
863 dmas = <&edma 10>,
864 <&edma 11>;
865 dma-names = "tx", "rx";
866 };
867
868 rng: rng@48310000 {
869 compatible = "ti,omap4-rng";
870 ti,hwmods = "rng";
871 reg = <0x48310000 0x2000>;
872 interrupts = <111>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]873 };
874 };
875};
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]876
877/include/ "am33xx-clocks.dtsi"