| Teresa Remmet | 30fb74d | 2021-01-13 16:28:09 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | * |
| 3 | * Copyright (C) 2020 PHYTEC Messtechnik GmbH |
| 4 | * Author: Teresa Remmet <t.remmet@phytec.de> |
| 5 | */ |
| 6 | |
| 7 | #ifndef __PHYCORE_IMX8MP_H |
| 8 | #define __PHYCORE_IMX8MP_H |
| 9 | |
| 10 | #include <linux/sizes.h> |
| 11 | #include <asm/arch/imx-regs.h> |
| 12 | |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 13 | #define CFG_SYS_UBOOT_BASE \ |
| Teresa Remmet | 30fb74d | 2021-01-13 16:28:09 +0100 | [diff] [blame] | 14 | (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) |
| 15 | |
| Teresa Remmet | 30fb74d | 2021-01-13 16:28:09 +0100 | [diff] [blame] | 16 | /* Link Definitions */ |
| Teresa Remmet | 30fb74d | 2021-01-13 16:28:09 +0100 | [diff] [blame] | 17 | |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 18 | #define CFG_SYS_INIT_RAM_ADDR 0x40000000 |
| 19 | #define CFG_SYS_INIT_RAM_SIZE SZ_512K |
| Teresa Remmet | 30fb74d | 2021-01-13 16:28:09 +0100 | [diff] [blame] | 20 | |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 21 | #define CFG_SYS_SDRAM_BASE 0x40000000 |
| Teresa Remmet | 30fb74d | 2021-01-13 16:28:09 +0100 | [diff] [blame] | 22 | |
| 23 | #define PHYS_SDRAM 0x40000000 |
| Teresa Remmet | fe55627 | 2024-05-28 15:35:13 +0200 | [diff] [blame] | 24 | #define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */ |
| 25 | #define PHYS_SDRAM_2 0x100000000 |
| 26 | #define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* 5GB */ |
| Teresa Remmet | 30fb74d | 2021-01-13 16:28:09 +0100 | [diff] [blame] | 27 | |
| Teresa Remmet | 30fb74d | 2021-01-13 16:28:09 +0100 | [diff] [blame] | 28 | #endif /* __PHYCORE_IMX8MP_H */ |