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git01.mediatek.com / filogic / uboot / b4ef5a1bb47ca90414ea77061161bd53f4a4dcad / . / configs / chromebook_kevin_defconfig
blob: 20913d2cf0fed0f4cc311664c5f61a760cdd04ef [file] [log] [blame]
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]1CONFIG_ARM=y
2CONFIG_SKIP_LOWLEVEL_INIT=y
Peng Fanc8a61c02022-04-13 17:47:20 +0800[diff] [blame]3CONFIG_COUNTER_FREQUENCY=24000000
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]4CONFIG_ARCH_ROCKCHIP=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]5CONFIG_TEXT_BASE=0x00200000
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]6CONFIG_SPL_GPIO=y
7CONFIG_NR_DRAM_BANKS=1
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]8CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
9CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
Tom Rinia77d6f82023-05-01 11:50:26 -0400[diff] [blame]10CONFIG_SF_DEFAULT_SPEED=20000000
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]11CONFIG_ENV_OFFSET=0x3F8000
12CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-kevin"
13CONFIG_SPL_TEXT_BASE=0xff8c2000
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]14CONFIG_DM_RESET=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]15CONFIG_ROCKCHIP_RK3399=y
16CONFIG_ROCKCHIP_BOOT_MODE_REG=0
17CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000
18# CONFIG_SPL_MMC is not set
19CONFIG_TARGET_CHROMEBOOK_KEVIN=y
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]20CONFIG_SPL_STACK=0xff8effff
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]21CONFIG_DEBUG_UART_BASE=0xff1a0000
22CONFIG_DEBUG_UART_CLOCK=24000000
23CONFIG_SPL_SPI_FLASH_SUPPORT=y
24CONFIG_SPL_SPI=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]25CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]26CONFIG_DEBUG_UART=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]27CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb"
28# CONFIG_DISPLAY_CPUINFO is not set
29CONFIG_DISPLAY_BOARDINFO_LATE=y
30CONFIG_BOARD_EARLY_INIT_R=y
31CONFIG_MISC_INIT_R=y
32CONFIG_BLOBLIST=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]33CONFIG_BLOBLIST_ADDR=0x100000
Tom Rini8f84e4e2022-03-28 14:01:11 +0000[diff] [blame]34CONFIG_BLOBLIST_SIZE=0x1000
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]35CONFIG_SPL_MAX_SIZE=0x2e000
36CONFIG_SPL_PAD_TO=0x7f8000
Tom Rini65aa1242022-05-27 10:19:45 -0400[diff] [blame]37CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
38CONFIG_SPL_BSS_START_ADDR=0xff8e0000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]39CONFIG_SPL_BSS_MAX_SIZE=0x10000
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]40CONFIG_HANDOFF=y
41# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]42# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]43CONFIG_SPL_STACK_R=y
44CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
45CONFIG_SPL_SPI_LOAD=y
46CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
Quentin Schulz95edee72023-06-21 18:02:52 +0200[diff] [blame]47CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]48CONFIG_CMD_BOOTZ=y
49CONFIG_CMD_GPIO=y
50CONFIG_CMD_GPT=y
51CONFIG_CMD_I2C=y
52CONFIG_CMD_MMC=y
53CONFIG_CMD_SF_TEST=y
54CONFIG_CMD_SPI=y
55CONFIG_CMD_USB=y
56# CONFIG_CMD_SETEXPR is not set
57CONFIG_CMD_TIME=y
58CONFIG_CMD_PMIC=y
59CONFIG_CMD_REGULATOR=y
60CONFIG_CMD_LOG=y
61CONFIG_SPL_OF_CONTROL=y
62CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
63CONFIG_ENV_IS_IN_MMC=y
64CONFIG_SYS_RELOC_GD_ENV_ADDR=y
65CONFIG_SPL_DM_SEQ_ALIAS=y
66CONFIG_ROCKCHIP_GPIO=y
67CONFIG_I2C_CROS_EC_TUNNEL=y
68CONFIG_SYS_I2C_ROCKCHIP=y
69CONFIG_I2C_MUX=y
70CONFIG_CROS_EC_KEYB=y
71CONFIG_MISC=y
72CONFIG_ROCKCHIP_EFUSE=y
73CONFIG_CROS_EC=y
74CONFIG_CROS_EC_SPI=y
75CONFIG_PWRSEQ=y
76CONFIG_MMC_PWRSEQ=y
77CONFIG_MMC_DW=y
78CONFIG_MMC_DW_ROCKCHIP=y
79CONFIG_MMC_SDHCI=y
80CONFIG_MMC_SDHCI_ROCKCHIP=y
81CONFIG_SF_DEFAULT_BUS=1
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]82CONFIG_SPI_FLASH_GIGADEVICE=y
83CONFIG_SPI_FLASH_WINBOND=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]84CONFIG_ETH_DESIGNWARE=y
85CONFIG_GMAC_ROCKCHIP=y
86CONFIG_PHY_ROCKCHIP_INNO_USB2=y
87CONFIG_PHY_ROCKCHIP_TYPEC=y
88CONFIG_PMIC_RK8XX=y
89CONFIG_REGULATOR_PWM=y
90CONFIG_DM_REGULATOR_GPIO=y
91CONFIG_REGULATOR_RK8XX=y
92CONFIG_PWM_CROS_EC=y
93CONFIG_PWM_ROCKCHIP=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]94CONFIG_DM_RNG=y
95CONFIG_RNG_ROCKCHIP=y
96CONFIG_DEBUG_UART_SHIFT=2
Tom Rinidc172ee2022-12-04 09:39:03 -0500[diff] [blame]97CONFIG_SYS_NS16550_MEM32=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]98CONFIG_ROCKCHIP_SPI=y
99CONFIG_SYSRESET=y
100CONFIG_USB=y
101CONFIG_USB_XHCI_HCD=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]102CONFIG_USB_EHCI_HCD=y
103CONFIG_USB_EHCI_GENERIC=y
104CONFIG_USB_OHCI_HCD=y
105CONFIG_USB_OHCI_GENERIC=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]106CONFIG_USB_DWC3=y
Jonas Karlmanac8d1572023-11-12 17:48:57 +0000[diff] [blame]107CONFIG_USB_DWC3_GENERIC=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]108CONFIG_USB_KEYBOARD=y
109CONFIG_USB_HOST_ETHER=y
110CONFIG_USB_ETHER_ASIX=y
111CONFIG_USB_ETHER_ASIX88179=y
112CONFIG_USB_ETHER_MCS7830=y
113CONFIG_USB_ETHER_RTL8152=y
114CONFIG_USB_ETHER_SMSC95XX=y
Simon Glass52cb5042022-10-18 07:46:31 -0600[diff] [blame]115CONFIG_VIDEO=y
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +0300[diff] [blame]116CONFIG_DISPLAY=y
117CONFIG_VIDEO_ROCKCHIP=y
118CONFIG_VIDEO_ROCKCHIP_MAX_XRES=2400
119CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1600
120CONFIG_DISPLAY_ROCKCHIP_EDP=y
121CONFIG_CMD_DHRYSTONE=y
122CONFIG_ERRNO_STR=y