blob: d78ee403e6ce6715801ada94a8a47cae77e4612a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Rick Chen36cb27c2017-12-26 13:55:53 +08002/*
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
Rick Chen36cb27c2017-12-26 13:55:53 +08005 */
6
Rick Chen36cb27c2017-12-26 13:55:53 +08007#include <common.h>
Yu Chien Peter Lin39689a92023-02-06 16:10:45 +08008#include <cpu_func.h>
Simon Glass8e201882020-05-10 11:39:54 -06009#include <flash.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060010#include <image.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -070011#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060012#include <net.h>
Rick Chen36cb27c2017-12-26 13:55:53 +080013#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
14#include <netdev.h>
15#endif
Simon Glass3ba929a2020-10-30 21:38:53 -060016#include <asm/global_data.h>
Rick Chen36cb27c2017-12-26 13:55:53 +080017#include <linux/io.h>
Rick Chencea16d02018-05-29 11:07:53 +080018#include <faraday/ftsmc020.h>
19#include <fdtdec.h>
Rick Chen9e017162019-08-28 18:46:07 +080020#include <dm.h>
Rick Chenc3027d02019-11-14 13:52:22 +080021#include <spl.h>
Randolphb4dc63f2023-10-12 14:35:09 +080022#include <mapmem.h>
23#include <hang.h>
Rick Chen36cb27c2017-12-26 13:55:53 +080024
25DECLARE_GLOBAL_DATA_PTR;
26
27/*
28 * Miscellaneous platform dependent initializations
29 */
30
Randolphb4dc63f2023-10-12 14:35:09 +080031#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
32#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x100000)
33void spl_perform_fixups(struct spl_image_info *spl_image)
34{
35 /*
36 * Originally, u-boot-spl will place DTB directly after the kernel,
37 * but the size of the kernel did not include the BSS section, which
38 * means u-boot-spl will place the DTB in the kernel BSS section
39 * causing the DTB to be cleared by kernel BSS initializtion.
40 * Moving DTB in front of the kernel can avoid the error.
41 */
42 if (ANDES_SPL_FDT_ADDR < 0) {
43 printf("%s: CONFIG_TEXT_BASE needs to be larger than 0x100000\n",
44 __func__);
45 hang();
46 }
47
48 memcpy((void *)ANDES_SPL_FDT_ADDR, spl_image->fdt_addr,
49 fdt_totalsize(spl_image->fdt_addr));
50 spl_image->fdt_addr = map_sysmem(ANDES_SPL_FDT_ADDR, 0);
51}
52#endif
53
Rick Chen36cb27c2017-12-26 13:55:53 +080054int board_init(void)
55{
Rick Chen36cb27c2017-12-26 13:55:53 +080056 gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
57
58 return 0;
59}
60
61int dram_init(void)
62{
Rick Chen92038262019-11-14 13:52:23 +080063 return fdtdec_setup_mem_size_base();
Rick Chen36cb27c2017-12-26 13:55:53 +080064}
65
66int dram_init_banksize(void)
67{
Rick Chen92038262019-11-14 13:52:23 +080068 return fdtdec_setup_memory_banksize();
Rick Chen36cb27c2017-12-26 13:55:53 +080069}
70
71#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090072int board_eth_init(struct bd_info *bd)
Rick Chen36cb27c2017-12-26 13:55:53 +080073{
74 return ftmac100_initialize(bd);
75}
76#endif
77
78ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
79{
80 return 0;
81}
Rick Chen40a6fe72018-03-29 10:08:33 +080082
Leo Yu-Chi Liang4150eec2022-06-01 10:01:49 +080083#define ANDES_HW_DTB_ADDRESS 0xF2000000
Ilias Apalodimasab5348a2021-10-26 09:12:33 +030084void *board_fdt_blob_setup(int *err)
Rick Chen40a6fe72018-03-29 10:08:33 +080085{
Ilias Apalodimasab5348a2021-10-26 09:12:33 +030086 *err = 0;
Leo Yu-Chi Liang4150eec2022-06-01 10:01:49 +080087
88 if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
Rick Chen206feaa2022-10-20 13:56:17 +080089 if (fdt_magic((uintptr_t)gd->arch.firmware_fdt_addr) == FDT_MAGIC)
Leo Yu-Chi Liang4150eec2022-06-01 10:01:49 +080090 return (void *)(ulong)gd->arch.firmware_fdt_addr;
91 }
92
93 if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC)
94 return (void *)CONFIG_SYS_FDT_BASE;
95 return (void *)ANDES_HW_DTB_ADDRESS;
96
Ilias Apalodimasab5348a2021-10-26 09:12:33 +030097 *err = -EINVAL;
Ilias Apalodimasdc35df42021-10-12 00:00:13 +030098 return NULL;
Rick Chen40a6fe72018-03-29 10:08:33 +080099}
Rick Chencea16d02018-05-29 11:07:53 +0800100
Yu Chien Peter Lin39689a92023-02-06 16:10:45 +0800101#ifdef CONFIG_SPL_BOARD_INIT
102void spl_board_init()
103{
104 /* enable v5l2 cache */
105 enable_caches();
106}
107#endif
108
Rick Chencea16d02018-05-29 11:07:53 +0800109int smc_init(void)
110{
111 int node = -1;
112 const char *compat = "andestech,atfsmc020";
113 void *blob = (void *)gd->fdt_blob;
114 fdt_addr_t addr;
115 struct ftsmc020_bank *regs;
116
117 node = fdt_node_offset_by_compatible(blob, -1, compat);
118 if (node < 0)
119 return -FDT_ERR_NOTFOUND;
120
Rick Chenca3e5e42020-07-17 16:24:44 +0800121 addr = fdtdec_get_addr_size_auto_noparent(blob, node,
122 "reg", 0, NULL, false);
Rick Chencea16d02018-05-29 11:07:53 +0800123
124 if (addr == FDT_ADDR_T_NONE)
125 return -EINVAL;
126
Bin Meng65d59952021-01-31 20:36:01 +0800127 regs = (struct ftsmc020_bank *)(uintptr_t)addr;
Rick Chencea16d02018-05-29 11:07:53 +0800128 regs->cr &= ~FTSMC020_BANK_WPROT;
129
130 return 0;
131}
132
133#ifdef CONFIG_BOARD_EARLY_INIT_F
134int board_early_init_f(void)
135{
136 smc_init();
137
138 return 0;
139}
140#endif
Rick Chenc3027d02019-11-14 13:52:22 +0800141
142#ifdef CONFIG_SPL
143void board_boot_order(u32 *spl_boot_list)
144{
145 u8 i;
146 u32 boot_devices[] = {
147#ifdef CONFIG_SPL_RAM_SUPPORT
148 BOOT_DEVICE_RAM,
149#endif
Simon Glassb58bfe02021-08-08 12:20:09 -0600150#ifdef CONFIG_SPL_MMC
Rick Chenc3027d02019-11-14 13:52:22 +0800151 BOOT_DEVICE_MMC1,
152#endif
153 };
154
155 for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
156 spl_boot_list[i] = boot_devices[i];
157}
158#endif
159
160#ifdef CONFIG_SPL_LOAD_FIT
161int board_fit_config_name_match(const char *name)
162{
163 /* boot using first FIT config */
164 return 0;
165}
166#endif