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git01.mediatek.com / filogic / uboot / b4b65ecba1a0fa4c0f22150737307a933a707b8b / . / arch / arm / dts / imx8mn-evk.dtsi
blob: 76d042a4cf092a457819d4a86893ca6d00a0c75d [file] [log] [blame]
Peng Fancdc90f32020-12-27 09:37:06 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/usb/pd.h>
7#include "imx8mn.dtsi"
8
9/ {
10 chosen {
11 stdout-path = &uart2;
12 };
13
14 gpio-leds {
15 compatible = "gpio-leds";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_led>;
18
19 status {
20 label = "yellow:status";
21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
22 default-state = "on";
23 };
24 };
25
26 memory@40000000 {
27 device_type = "memory";
28 reg = <0x0 0x40000000 0 0x80000000>;
29 };
30
31 reg_usdhc2_vmmc: regulator-usdhc2 {
32 compatible = "regulator-fixed";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
35 regulator-name = "VSD_3V3";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
39 enable-active-high;
40 };
41
42 ir-receiver {
43 compatible = "gpio-ir-receiver";
44 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_ir>;
47 linux,autosuspend-period = <125>;
48 };
49};
50
51&fec1 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_fec1>;
54 phy-mode = "rgmii-id";
55 phy-handle = <&ethphy0>;
56 fsl,magic-packet;
57 status = "okay";
58
59 mdio {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 ethphy0: ethernet-phy@0 {
64 compatible = "ethernet-phy-ieee802.3-c22";
65 reg = <0>;
66 };
67 };
68};
69
70&i2c1 {
71 clock-frequency = <400000>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_i2c1>;
74 status = "okay";
75};
76
77&i2c2 {
78 clock-frequency = <400000>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_i2c2>;
81 status = "okay";
82
83 ptn5110: tcpc@50 {
84 compatible = "nxp,ptn5110";
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_typec1>;
87 reg = <0x50>;
88 interrupt-parent = <&gpio2>;
89 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
90 status = "okay";
91
92 port {
93 typec1_dr_sw: endpoint {
94 remote-endpoint = <&usb1_drd_sw>;
95 };
96 };
97
98 typec1_con: connector {
99 compatible = "usb-c-connector";
100 label = "USB-C";
101 power-role = "dual";
102 data-role = "dual";
103 try-power-role = "sink";
104 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
105 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
106 PDO_VAR(5000, 20000, 3000)>;
107 op-sink-microwatt = <15000000>;
108 self-powered;
109 };
110 };
111};
112
113&i2c3 {
114 clock-frequency = <400000>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_i2c3>;
117 status = "okay";
118
119 pca6416: gpio@20 {
120 compatible = "ti,tca6416";
121 reg = <0x20>;
122 gpio-controller;
123 #gpio-cells = <2>;
124 };
125};
126
127&snvs_pwrkey {
128 status = "okay";
129};
130
131&uart2 { /* console */
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_uart2>;
134 status = "okay";
135};
136
137&usbotg1 {
138 dr_mode = "otg";
139 hnp-disable;
140 srp-disable;
141 adp-disable;
142 usb-role-switch;
143 samsung,picophy-pre-emp-curr-control = <3>;
144 samsung,picophy-dc-vol-level-adjust = <7>;
145 status = "okay";
146
147 port {
148 usb1_drd_sw: endpoint {
149 remote-endpoint = <&typec1_dr_sw>;
150 };
151 };
152};
153
154&usdhc2 {
155 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
156 assigned-clock-rates = <200000000>;
157 pinctrl-names = "default", "state_100mhz", "state_200mhz";
158 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
159 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
160 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
161 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
162 bus-width = <4>;
163 vmmc-supply = <&reg_usdhc2_vmmc>;
164 status = "okay";
165};
166
167&usdhc3 {
168 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
169 assigned-clock-rates = <400000000>;
170 pinctrl-names = "default", "state_100mhz", "state_200mhz";
171 pinctrl-0 = <&pinctrl_usdhc3>;
172 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
173 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
174 bus-width = <8>;
175 non-removable;
176 status = "okay";
177};
178
179&wdog1 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_wdog>;
182 fsl,ext-reset-output;
183 status = "okay";
184};
185
186&iomuxc {
187 pinctrl_fec1: fec1grp {
188 fsl,pins = <
189 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
190 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
191 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
192 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
193 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
194 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
195 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
196 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
197 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
198 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
199 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
200 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
201 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
202 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
203 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
204 >;
205 };
206
207 pinctrl_gpio_led: gpioledgrp {
208 fsl,pins = <
209 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
210 >;
211 };
212
213 pinctrl_ir: irgrp {
214 fsl,pins = <
215 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
216 >;
217 };
218
219 pinctrl_i2c1: i2c1grp {
220 fsl,pins = <
221 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
222 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
223 >;
224 };
225
226 pinctrl_i2c2: i2c2grp {
227 fsl,pins = <
228 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
229 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
230 >;
231 };
232
233 pinctrl_i2c3: i2c3grp {
234 fsl,pins = <
235 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
236 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
237 >;
238 };
239
240 pinctrl_pmic: pmicirqgrp {
241 fsl,pins = <
242 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
243 >;
244 };
245
246 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
247 fsl,pins = <
248 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
249 >;
250 };
251
252 pinctrl_typec1: typec1grp {
253 fsl,pins = <
254 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
255 >;
256 };
257
258 pinctrl_uart2: uart2grp {
259 fsl,pins = <
260 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
261 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
262 >;
263 };
264
265 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
266 fsl,pins = <
267 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
268 >;
269 };
270
271 pinctrl_usdhc2: usdhc2grp {
272 fsl,pins = <
273 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
274 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
275 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
276 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
277 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
278 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
279 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
280 >;
281 };
282
283 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
284 fsl,pins = <
285 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
286 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
287 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
288 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
289 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
290 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
291 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
292 >;
293 };
294
295 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
296 fsl,pins = <
297 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
298 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
299 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
300 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
301 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
302 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
303 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
304 >;
305 };
306
307 pinctrl_usdhc3: usdhc3grp {
308 fsl,pins = <
309 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
310 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
311 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
312 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
313 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
314 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
315 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
316 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
317 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
318 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
319 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
320 >;
321 };
322
323 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
324 fsl,pins = <
325 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
326 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
327 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
328 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
329 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
330 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
331 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
332 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
333 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
334 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
335 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
336 >;
337 };
338
339 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
340 fsl,pins = <
341 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
342 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
343 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
344 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
345 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
346 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
347 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
348 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
349 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
350 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
351 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
352 >;
353 };
354
355 pinctrl_wdog: wdoggrp {
356 fsl,pins = <
357 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
358 >;
359 };
360};