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git01.mediatek.com / filogic / uboot / b469006bef67c6167771346322148f60ea34794f / . / arch / arm / mach-imx / speed.c
blob: e78b1fd71b6e0e7f78c800aeb059bb6eb24bdc34 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]2/*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]8 */
9
10#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -0700[diff] [blame]11#include <clock_legacy.h>
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]12#include <asm/arch/imx-regs.h>
Stefano Babicac41d4d2010-03-05 17:54:37 +0100[diff] [blame]13#include <asm/arch/clock.h>
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]14
Yangbo Lu73340382019-06-21 11:42:28 +0800[diff] [blame]15#ifdef CONFIG_FSL_ESDHC_IMX
John Rigby0d21ed02010-12-20 18:27:51 -0700[diff] [blame]16DECLARE_GLOBAL_DATA_PTR;
17#endif
18
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]19int get_clocks(void)
20{
Yangbo Lu73340382019-06-21 11:42:28 +0800[diff] [blame]21#ifdef CONFIG_FSL_ESDHC_IMX
Michael Langerb2ec8162012-06-14 03:44:33 +0000[diff] [blame]22#ifdef CONFIG_FSL_USDHC
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]23#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]24 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]25#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]26 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]27#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]28 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]29#else
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]30 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]31#endif
Michael Langerb2ec8162012-06-14 03:44:33 +0000[diff] [blame]32#else
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]33#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]34 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]35#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]36 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]37#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]38 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]39#else
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]40 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]41#endif
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]42#endif
Michael Langerb2ec8162012-06-14 03:44:33 +0000[diff] [blame]43#endif
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]44 return 0;
45}