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git01.mediatek.com / filogic / uboot / b4680cadd5bb59ba1ee85a22e3bc6ee13e2db8ce / . / drivers / ddr / fsl / Kconfig
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York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]1config SYS_FSL_DDR
2 bool
3 help
4 Select Freescale General DDR driver, shared between most Freescale
5 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
6 based Layerscape SoCs (such as ls2080a).
7
8config SYS_FSL_MMDC
9 bool
10 help
11 Select Freescale Multi Mode DDR controller (MMDC).
12
13config SYS_FSL_DDR_BE
14 bool
15 help
16 Access DDR registers in big-endian
17
18config SYS_FSL_DDR_LE
19 bool
20 help
21 Access DDR registers in little-endian
22
23menu "Freescale DDR controllers"
24 depends on SYS_FSL_DDR
25
York Sunfe845072016-12-28 08:43:45 -0800[diff] [blame]26config SYS_NUM_DDR_CTLRS
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]27 int "Maximum DDR controllers"
28 default 3 if ARCH_LS2080A || \
29 ARCH_T4240
30 default 2 if ARCH_B4860 || \
31 ARCH_BSC9132 || \
32 ARCH_MPC8572 || \
33 ARCH_MPC8641 || \
34 ARCH_P4080 || \
35 ARCH_P5020 || \
36 ARCH_P5040 || \
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000[diff] [blame]37 ARCH_LX2160A || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]38 ARCH_T4160
39 default 1
40
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]41config SYS_FSL_DDR_VER
42 int
43 default 50 if SYS_FSL_DDR_VER_50
44 default 47 if SYS_FSL_DDR_VER_47
45 default 46 if SYS_FSL_DDR_VER_46
46 default 44 if SYS_FSL_DDR_VER_44
47
48config SYS_FSL_DDR_VER_50
49 bool
50
51config SYS_FSL_DDR_VER_47
52 bool
53
54config SYS_FSL_DDR_VER_46
55 bool
56
57config SYS_FSL_DDR_VER_44
58 bool
59
60config SYS_FSL_DDRC_GEN1
61 bool
62 help
63 Enable Freescale DDR controller.
64
65config SYS_FSL_DDRC_GEN2
66 bool
67 depends on !MPC86xx
68 help
69 Enable Freescale DDR2 controller.
70
71config SYS_FSL_DDRC_86XX_GEN2
72 bool
73 depends on MPC86xx
74 help
75 Enable Freescale DDR2 controller for MPC86xx SoCs.
76
77config SYS_FSL_DDRC_GEN3
78 bool
79 depends on PPC
80 help
81 Enable Freescale DDR3 controller for PowerPC SoCs.
82
83config SYS_FSL_DDRC_ARM_GEN3
84 bool
85 depends on ARM
86 help
87 Enable Freescale DDR3 controller for ARM SoCs.
88
89config SYS_FSL_DDRC_GEN4
90 bool
91 help
92 Enable Freescale DDR4 controller.
93
94config SYS_FSL_HAS_DDR4
95 bool
96
97config SYS_FSL_HAS_DDR3
98 bool
99
100config SYS_FSL_HAS_DDR2
101 bool
102
103config SYS_FSL_HAS_DDR1
104 bool
105
106choice
107 prompt "DDR technology"
108 default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
109 default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
110 default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
111 default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
112
113config SYS_FSL_DDR4
114 bool "Freescale DDR4 controller"
115 depends on SYS_FSL_HAS_DDR4
116 select SYS_FSL_DDRC_GEN4
117
118config SYS_FSL_DDR3
119 bool "Freescale DDR3 controller"
120 depends on SYS_FSL_HAS_DDR3
121 select SYS_FSL_DDRC_GEN3 if PPC
122 select SYS_FSL_DDRC_ARM_GEN3 if ARM
123
124config SYS_FSL_DDR2
125 bool "Freescale DDR2 controller"
126 depends on SYS_FSL_HAS_DDR2
127 select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
128 select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx
129
130config SYS_FSL_DDR1
131 bool "Freescale DDR1 controller"
132 depends on SYS_FSL_HAS_DDR1
133 select SYS_FSL_DDRC_GEN1
134
135endchoice
136
137endmenu
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]138
139config SYS_FSL_ERRATUM_A008378
140 bool
141
142config SYS_FSL_ERRATUM_A008511
143 bool
144
145config SYS_FSL_ERRATUM_A009663
146 bool
147
148config SYS_FSL_ERRATUM_A009801
149 bool
150
151config SYS_FSL_ERRATUM_A009803
152 bool
153
154config SYS_FSL_ERRATUM_A009942
155 bool
156
157config SYS_FSL_ERRATUM_A010165
158 bool
York Sunbe735532016-12-28 08:43:43 -0800[diff] [blame]159
160config SYS_FSL_ERRATUM_NMG_DDR120
161 bool
162
163config SYS_FSL_ERRATUM_DDR_115
164 bool
165
166config SYS_FSL_ERRATUM_DDR111_DDR134
167 bool
168
169config SYS_FSL_ERRATUM_DDR_A003
170 bool
171
172config SYS_FSL_ERRATUM_DDR_A003474
173 bool