Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / b464044f6ee1de0c2643e1baea7317a2b1cc5963 / . / configs / anbernic-rgxx3-rk3566_defconfig
blob: ed6643d9d4fab590077b6425ca8851df1b2e917b [file] [log] [blame]
Chris Morgan8c4e3042023-04-21 10:59:19 -0500[diff] [blame]1CONFIG_ARM=y
2CONFIG_SKIP_LOWLEVEL_INIT=y
3CONFIG_COUNTER_FREQUENCY=24000000
4CONFIG_ARCH_ROCKCHIP=y
5CONFIG_TEXT_BASE=0x00a00000
6CONFIG_SPL_LIBCOMMON_SUPPORT=y
7CONFIG_SPL_LIBGENERIC_SUPPORT=y
8CONFIG_NR_DRAM_BANKS=2
9CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
10CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
11CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3"
12CONFIG_ROCKCHIP_RK3568=y
13CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
14CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
Chris Morgan27aad072023-05-15 11:00:31 -0500[diff] [blame]15CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y
Chris Morgan8c4e3042023-04-21 10:59:19 -0500[diff] [blame]16CONFIG_SPL_MMC=y
17CONFIG_SPL_SERIAL=y
18CONFIG_SPL_STACK_R_ADDR=0x600000
19CONFIG_TARGET_ANBERNIC_RGXX3_RK3566=y
20CONFIG_SPL_STACK=0x400000
21CONFIG_DEBUG_UART_BASE=0xFE660000
22CONFIG_DEBUG_UART_CLOCK=24000000
23CONFIG_SYS_LOAD_ADDR=0xc00800
24CONFIG_DEBUG_UART=y
25CONFIG_FIT=y
26CONFIG_FIT_VERBOSE=y
27CONFIG_SPL_LOAD_FIT=y
Chris Morgan27aad072023-05-15 11:00:31 -0500[diff] [blame]28CONFIG_OF_BOARD_SETUP=y
29CONFIG_OF_STDOUT_VIA_ALIAS=y
Chris Morgan8c4e3042023-04-21 10:59:19 -0500[diff] [blame]30CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb"
Chris Morgan27aad072023-05-15 11:00:31 -0500[diff] [blame]31# CONFIG_CONSOLE_MUX is not set
Chris Morgan8c4e3042023-04-21 10:59:19 -0500[diff] [blame]32# CONFIG_DISPLAY_CPUINFO is not set
33CONFIG_DISPLAY_BOARDINFO_LATE=y
Chris Morgan27aad072023-05-15 11:00:31 -0500[diff] [blame]34CONFIG_BOARD_RNG_SEED=y
Chris Morgan8c4e3042023-04-21 10:59:19 -0500[diff] [blame]35CONFIG_SPL_MAX_SIZE=0x20000
36CONFIG_SPL_PAD_TO=0x7f8000
37CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
38CONFIG_SPL_BSS_START_ADDR=0x4000000
39CONFIG_SPL_BSS_MAX_SIZE=0x4000
40CONFIG_SPL_BOARD_INIT=y
41# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
42# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
43CONFIG_SPL_STACK_R=y
44CONFIG_SPL_ATF=y
45CONFIG_CMD_PWM=y
46CONFIG_CMD_GPT=y
47CONFIG_CMD_MMC=y
48# CONFIG_CMD_SETEXPR is not set
Chris Morgan27aad072023-05-15 11:00:31 -0500[diff] [blame]49# CONFIG_CMD_CLS is not set
Chris Morgan8c4e3042023-04-21 10:59:19 -0500[diff] [blame]50# CONFIG_SPL_DOS_PARTITION is not set
51CONFIG_SPL_OF_CONTROL=y
52CONFIG_OF_LIVE=y
53CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
54# CONFIG_NET is not set
55CONFIG_SPL_REGMAP=y
56CONFIG_SPL_SYSCON=y
57CONFIG_SPL_CLK=y
58CONFIG_ARM_SMCCC_FEATURES=y
59CONFIG_SCMI_FIRMWARE=y
60CONFIG_ROCKCHIP_GPIO=y
61CONFIG_SYS_I2C_ROCKCHIP=y
62CONFIG_MISC=y
63CONFIG_SUPPORT_EMMC_RPMB=y
64CONFIG_MMC_DW=y
65CONFIG_MMC_DW_ROCKCHIP=y
66CONFIG_MMC_SDHCI=y
67CONFIG_MMC_SDHCI_SDMA=y
68CONFIG_MMC_SDHCI_ROCKCHIP=y
Chris Morgan27aad072023-05-15 11:00:31 -0500[diff] [blame]69CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
Chris Morgan8c4e3042023-04-21 10:59:19 -0500[diff] [blame]70CONFIG_DM_PMIC=y
71CONFIG_DM_PMIC_FAN53555=y
72CONFIG_PMIC_RK8XX=y
73CONFIG_REGULATOR_PWM=y
74CONFIG_DM_REGULATOR_GPIO=y
75CONFIG_REGULATOR_RK8XX=y
76CONFIG_DM_REGULATOR_SCMI=y
77CONFIG_PWM_ROCKCHIP=y
78CONFIG_SPL_RAM=y
Chris Morgan27aad072023-05-15 11:00:31 -0500[diff] [blame]79# CONFIG_RAM_ROCKCHIP_DEBUG is not set
80CONFIG_DM_RNG=y
81CONFIG_RNG_ROCKCHIP=y
82# CONFIG_RNG_SMCCC_TRNG is not set
Chris Morgan8c4e3042023-04-21 10:59:19 -0500[diff] [blame]83CONFIG_BAUDRATE=1500000
84CONFIG_DEBUG_UART_SHIFT=2
85CONFIG_SYS_NS16550_MEM32=y
86CONFIG_SYSRESET=y
Chris Morgan27aad072023-05-15 11:00:31 -0500[diff] [blame]87CONFIG_VIDEO=y
88CONFIG_VIDEO_ROCKCHIP=y
89CONFIG_DISPLAY_ROCKCHIP_DW_MIPI=y
90CONFIG_VIDEO_BRIDGE=y
Chris Morgan8c4e3042023-04-21 10:59:19 -0500[diff] [blame]91CONFIG_REGEX=y
92CONFIG_ERRNO_STR=y
93# CONFIG_EFI_LOADER is not set