| Manivannan Sadhasivam | 6f219a1 | 2018-09-28 00:32:59 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
| 4 | */ |
| Jagan Teki | dfe0a3d | 2020-05-09 22:26:24 +0530 | [diff] [blame] | 5 | |
| 6 | #include <common.h> |
| 7 | #include <syscon.h> |
| Jagan Teki | dfe0a3d | 2020-05-09 22:26:24 +0530 | [diff] [blame] | 8 | #include <asm/arch-rockchip/clock.h> |
| 9 | #include <asm/arch-rockchip/grf_rk3399.h> |
| 10 | #include <asm/arch-rockchip/hardware.h> |
| 11 | #include <linux/bitops.h> |
| 12 | |
| 13 | #ifdef CONFIG_MISC_INIT_R |
| 14 | int misc_init_r(void) |
| 15 | { |
| 16 | struct rk3399_grf_regs *grf = |
| 17 | syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
| 18 | |
| 19 | /** |
| 20 | * Some SSD's to work on rock960 would require explicit |
| 21 | * domain voltage change, so BT565 is in 1.8v domain |
| 22 | */ |
| 23 | rk_setreg(&grf->io_vsel, BIT(0)); |
| 24 | |
| 25 | return 0; |
| 26 | } |
| 27 | #endif |