Simon Glass | 8fbf992 | 2019-01-21 14:53:36 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2018 Google |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Alper Nebi Yasak | f55f388 | 2020-10-28 00:15:11 +0300 | [diff] [blame] | 7 | #include <dm.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 8 | #include <init.h> |
Alper Nebi Yasak | 437fa8d | 2021-12-24 16:43:43 +0300 | [diff] [blame] | 9 | #include <syscon.h> |
Alper Nebi Yasak | 437fa8d | 2021-12-24 16:43:43 +0300 | [diff] [blame] | 10 | #include <asm/arch-rockchip/clock.h> |
| 11 | #include <asm/arch-rockchip/grf_rk3399.h> |
| 12 | #include <asm/arch-rockchip/hardware.h> |
Alper Nebi Yasak | 437fa8d | 2021-12-24 16:43:43 +0300 | [diff] [blame] | 13 | |
| 14 | #define GRF_IO_VSEL_BT656_SHIFT 0 |
| 15 | #define GRF_IO_VSEL_AUDIO_SHIFT 1 |
| 16 | #define PMUGRF_CON0_VSEL_SHIFT 8 |
| 17 | #define PMUGRF_CON0_VOL_SHIFT 9 |
Simon Glass | 8fbf992 | 2019-01-21 14:53:36 -0700 | [diff] [blame] | 18 | |
Kever Yang | b22e9fd | 2019-07-22 19:59:41 +0800 | [diff] [blame] | 19 | #ifdef CONFIG_SPL_BUILD |
Simon Glass | 8fbf992 | 2019-01-21 14:53:36 -0700 | [diff] [blame] | 20 | /* provided to defeat compiler optimisation in board_init_f() */ |
| 21 | void gru_dummy_function(int i) |
| 22 | { |
| 23 | } |
Kever Yang | b22e9fd | 2019-07-22 19:59:41 +0800 | [diff] [blame] | 24 | |
| 25 | int board_early_init_f(void) |
| 26 | { |
Marty E. Plummer | b20a8dac | 2021-12-24 16:43:46 +0300 | [diff] [blame] | 27 | # if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN) |
Kever Yang | b22e9fd | 2019-07-22 19:59:41 +0800 | [diff] [blame] | 28 | int sum, i; |
| 29 | |
| 30 | /* |
| 31 | * Add a delay and ensure that the compiler does not optimise this out. |
| 32 | * This is needed since the power rails tail a while to turn on, and |
| 33 | * we get garbage serial output otherwise. |
| 34 | */ |
| 35 | sum = 0; |
| 36 | for (i = 0; i < 150000; i++) |
| 37 | sum += i; |
| 38 | gru_dummy_function(sum); |
| 39 | #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ |
| 40 | |
| 41 | return 0; |
| 42 | } |
| 43 | #endif |
Alper Nebi Yasak | f55f388 | 2020-10-28 00:15:11 +0300 | [diff] [blame] | 44 | |
| 45 | #ifndef CONFIG_SPL_BUILD |
| 46 | int board_early_init_r(void) |
| 47 | { |
| 48 | struct udevice *clk; |
| 49 | int ret; |
| 50 | |
| 51 | /* |
| 52 | * This init is done in SPL, but when chain-loading U-Boot SPL will |
| 53 | * have been skipped. Allow the clock driver to check if it needs |
| 54 | * setting up. |
| 55 | */ |
| 56 | ret = uclass_get_device_by_driver(UCLASS_CLK, |
Simon Glass | 65130cd | 2020-12-28 20:34:56 -0700 | [diff] [blame] | 57 | DM_DRIVER_GET(clk_rk3399), &clk); |
Alper Nebi Yasak | f55f388 | 2020-10-28 00:15:11 +0300 | [diff] [blame] | 58 | if (ret) { |
| 59 | debug("%s: CLK init failed: %d\n", __func__, ret); |
| 60 | return ret; |
| 61 | } |
| 62 | |
| 63 | return 0; |
| 64 | } |
| 65 | #endif |
Alper Nebi Yasak | 437fa8d | 2021-12-24 16:43:43 +0300 | [diff] [blame] | 66 | |
| 67 | static void setup_iodomain(void) |
| 68 | { |
| 69 | struct rk3399_grf_regs *grf = |
| 70 | syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
| 71 | struct rk3399_pmugrf_regs *pmugrf = |
| 72 | syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); |
| 73 | |
| 74 | /* BT656 and audio is in 1.8v domain */ |
| 75 | rk_setreg(&grf->io_vsel, (1 << GRF_IO_VSEL_BT656_SHIFT | |
| 76 | 1 << GRF_IO_VSEL_AUDIO_SHIFT)); |
| 77 | |
| 78 | /* |
| 79 | * Set GPIO1 1.8v/3.0v source select to PMU1830_VOL |
| 80 | * and explicitly configure that PMU1830_VOL to be 1.8V |
| 81 | */ |
| 82 | rk_setreg(&pmugrf->soc_con0, (1 << PMUGRF_CON0_VSEL_SHIFT | |
| 83 | 1 << PMUGRF_CON0_VOL_SHIFT)); |
| 84 | } |
| 85 | |
Quentin Schulz | 6e65ce1 | 2024-03-11 13:01:46 +0100 | [diff] [blame] | 86 | int rockchip_early_misc_init_r(void) |
Alper Nebi Yasak | 437fa8d | 2021-12-24 16:43:43 +0300 | [diff] [blame] | 87 | { |
Alper Nebi Yasak | 437fa8d | 2021-12-24 16:43:43 +0300 | [diff] [blame] | 88 | setup_iodomain(); |
| 89 | |
Quentin Schulz | 6e65ce1 | 2024-03-11 13:01:46 +0100 | [diff] [blame] | 90 | return 0; |
Alper Nebi Yasak | 437fa8d | 2021-12-24 16:43:43 +0300 | [diff] [blame] | 91 | } |