blob: 9cb3a52520473f109c7179f567915a1afb0759e0 [file] [log] [blame]
Simon Glass8fbf9922019-01-21 14:53:36 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 Google
4 */
5
6#include <common.h>
Alper Nebi Yasakf55f3882020-10-28 00:15:11 +03007#include <dm.h>
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
Alper Nebi Yasak437fa8d2021-12-24 16:43:43 +03009#include <syscon.h>
Alper Nebi Yasak437fa8d2021-12-24 16:43:43 +030010#include <asm/arch-rockchip/clock.h>
11#include <asm/arch-rockchip/grf_rk3399.h>
12#include <asm/arch-rockchip/hardware.h>
Alper Nebi Yasak437fa8d2021-12-24 16:43:43 +030013
14#define GRF_IO_VSEL_BT656_SHIFT 0
15#define GRF_IO_VSEL_AUDIO_SHIFT 1
16#define PMUGRF_CON0_VSEL_SHIFT 8
17#define PMUGRF_CON0_VOL_SHIFT 9
Simon Glass8fbf9922019-01-21 14:53:36 -070018
Kever Yangb22e9fd2019-07-22 19:59:41 +080019#ifdef CONFIG_SPL_BUILD
Simon Glass8fbf9922019-01-21 14:53:36 -070020/* provided to defeat compiler optimisation in board_init_f() */
21void gru_dummy_function(int i)
22{
23}
Kever Yangb22e9fd2019-07-22 19:59:41 +080024
25int board_early_init_f(void)
26{
Marty E. Plummerb20a8dac2021-12-24 16:43:46 +030027# if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN)
Kever Yangb22e9fd2019-07-22 19:59:41 +080028 int sum, i;
29
30 /*
31 * Add a delay and ensure that the compiler does not optimise this out.
32 * This is needed since the power rails tail a while to turn on, and
33 * we get garbage serial output otherwise.
34 */
35 sum = 0;
36 for (i = 0; i < 150000; i++)
37 sum += i;
38 gru_dummy_function(sum);
39#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
40
41 return 0;
42}
43#endif
Alper Nebi Yasakf55f3882020-10-28 00:15:11 +030044
45#ifndef CONFIG_SPL_BUILD
46int board_early_init_r(void)
47{
48 struct udevice *clk;
49 int ret;
50
51 /*
52 * This init is done in SPL, but when chain-loading U-Boot SPL will
53 * have been skipped. Allow the clock driver to check if it needs
54 * setting up.
55 */
56 ret = uclass_get_device_by_driver(UCLASS_CLK,
Simon Glass65130cd2020-12-28 20:34:56 -070057 DM_DRIVER_GET(clk_rk3399), &clk);
Alper Nebi Yasakf55f3882020-10-28 00:15:11 +030058 if (ret) {
59 debug("%s: CLK init failed: %d\n", __func__, ret);
60 return ret;
61 }
62
63 return 0;
64}
65#endif
Alper Nebi Yasak437fa8d2021-12-24 16:43:43 +030066
67static void setup_iodomain(void)
68{
69 struct rk3399_grf_regs *grf =
70 syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
71 struct rk3399_pmugrf_regs *pmugrf =
72 syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
73
74 /* BT656 and audio is in 1.8v domain */
75 rk_setreg(&grf->io_vsel, (1 << GRF_IO_VSEL_BT656_SHIFT |
76 1 << GRF_IO_VSEL_AUDIO_SHIFT));
77
78 /*
79 * Set GPIO1 1.8v/3.0v source select to PMU1830_VOL
80 * and explicitly configure that PMU1830_VOL to be 1.8V
81 */
82 rk_setreg(&pmugrf->soc_con0, (1 << PMUGRF_CON0_VSEL_SHIFT |
83 1 << PMUGRF_CON0_VOL_SHIFT));
84}
85
Quentin Schulz6e65ce12024-03-11 13:01:46 +010086int rockchip_early_misc_init_r(void)
Alper Nebi Yasak437fa8d2021-12-24 16:43:43 +030087{
Alper Nebi Yasak437fa8d2021-12-24 16:43:43 +030088 setup_iodomain();
89
Quentin Schulz6e65ce12024-03-11 13:01:46 +010090 return 0;
Alper Nebi Yasak437fa8d2021-12-24 16:43:43 +030091}