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wdenk1ebf41e2004-01-02 14:00:00 +00001/*
wdenk8d5d28a2005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenk1ebf41e2004-01-02 14:00:00 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkb50cde52004-01-24 20:25:54 +000015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk1ebf41e2004-01-02 14:00:00 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
37#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
38
wdenk20bddb32004-09-28 17:59:53 +000039#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
40#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
41#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
42#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
wdenkb50cde52004-01-24 20:25:54 +000043 /* (it will be used if there is no */
44 /* 'cpuclk' variable with valid value) */
wdenk1ebf41e2004-01-02 14:00:00 +000045
wdenkfde37042004-01-31 20:06:54 +000046#undef CFG_MEASURE_CPUCLK /* Measure real cpu clock */
47 /* (function measure_gclk() */
48 /* will be called) */
49#ifdef CFG_MEASURE_CPUCLK
50#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */
51#endif
52
wdenkb50cde52004-01-24 20:25:54 +000053#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
wdenk1ebf41e2004-01-02 14:00:00 +000054
55#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
56
wdenkb50cde52004-01-24 20:25:54 +000057#define CONFIG_BOOTCOUNT_LIMIT
wdenk1ebf41e2004-01-02 14:00:00 +000058
59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60
61#define CONFIG_BOARD_TYPES 1 /* support board types */
62
wdenkb50cde52004-01-24 20:25:54 +000063#define CONFIG_PREBOOT "echo;" \
wdenk1ebf41e2004-01-02 14:00:00 +000064 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
65 "echo"
66
67#undef CONFIG_BOOTARGS
68
wdenkb50cde52004-01-24 20:25:54 +000069#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk1ebf41e2004-01-02 14:00:00 +000070 "netdev=eth0\0" \
71 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010072 "nfsroot=${serverip}:${rootpath}\0" \
wdenk1ebf41e2004-01-02 14:00:00 +000073 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010074 "addip=setenv bootargs ${bootargs} " \
75 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
76 ":${hostname}:${netdev}:off panic=1\0" \
wdenk1ebf41e2004-01-02 14:00:00 +000077 "flash_nfs=run nfsargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010078 "bootm ${kernel_addr}\0" \
wdenk1ebf41e2004-01-02 14:00:00 +000079 "flash_self=run ramargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010080 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
81 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk1ebf41e2004-01-02 14:00:00 +000082 "rootpath=/opt/eldk/ppc_8xx\0" \
wdenkec342722004-01-31 20:13:31 +000083 "bootfile=/tftpboot/TQM866M/uImage\0" \
wdenk1ebf41e2004-01-02 14:00:00 +000084 "kernel_addr=40080000\0" \
85 "ramdisk_addr=40180000\0" \
86 ""
87#define CONFIG_BOOTCOMMAND "run flash_self"
88
89#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
90#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
91
92#undef CONFIG_WATCHDOG /* watchdog disabled */
93
wdenkb50cde52004-01-24 20:25:54 +000094#define CONFIG_STATUS_LED 1 /* Status LED enabled */
wdenk1ebf41e2004-01-02 14:00:00 +000095
96#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
97
98/* enable I2C and select the hardware/software driver */
99#undef CONFIG_HARD_I2C /* I2C with hardware support */
wdenkb50cde52004-01-24 20:25:54 +0000100#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
wdenk1ebf41e2004-01-02 14:00:00 +0000101
102#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
103#define CFG_I2C_SLAVE 0xFE
104
105#ifdef CONFIG_SOFT_I2C
106/*
107 * Software (bit-bang) I2C driver configuration
108 */
109#define PB_SCL 0x00000020 /* PB 26 */
110#define PB_SDA 0x00000010 /* PB 27 */
111
112#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
113#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
114#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
115#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
116#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
wdenkb50cde52004-01-24 20:25:54 +0000117 else immr->im_cpm.cp_pbdat &= ~PB_SDA
wdenk1ebf41e2004-01-02 14:00:00 +0000118#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
wdenkb50cde52004-01-24 20:25:54 +0000119 else immr->im_cpm.cp_pbdat &= ~PB_SCL
wdenk1ebf41e2004-01-02 14:00:00 +0000120#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
121#endif /* CONFIG_SOFT_I2C */
122
123#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
wdenkb50cde52004-01-24 20:25:54 +0000124#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
wdenk1ebf41e2004-01-02 14:00:00 +0000125#define CFG_EEPROM_PAGE_WRITE_BITS 4
126#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
127
128#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
129
130#define CONFIG_MAC_PARTITION
131#define CONFIG_DOS_PARTITION
132
wdenk4b6e9052004-02-06 21:48:22 +0000133#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
134
135#define CONFIG_TIMESTAMP /* but print image timestmps */
wdenk1ebf41e2004-01-02 14:00:00 +0000136
137#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
138 CFG_CMD_ASKENV | \
139 CFG_CMD_DHCP | \
140 CFG_CMD_EEPROM | \
wdenk8d5d28a2005-04-02 22:37:54 +0000141 CFG_CMD_I2C | \
wdenk1ebf41e2004-01-02 14:00:00 +0000142 CFG_CMD_IDE | \
wdenk8d414a72005-06-10 10:00:19 +0000143 CFG_CMD_NFS )
wdenk1ebf41e2004-01-02 14:00:00 +0000144
145/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
146#include <cmd_confdefs.h>
147
148/*
149 * Miscellaneous configurable options
150 */
wdenkb50cde52004-01-24 20:25:54 +0000151#define CFG_LONGHELP /* undef to save memory */
152#define CFG_PROMPT "=> " /* Monitor Command Prompt */
wdenk1ebf41e2004-01-02 14:00:00 +0000153
154#if 0
wdenkb50cde52004-01-24 20:25:54 +0000155#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
wdenk1ebf41e2004-01-02 14:00:00 +0000156#endif
157#ifdef CFG_HUSH_PARSER
wdenkb50cde52004-01-24 20:25:54 +0000158#define CFG_PROMPT_HUSH_PS2 "> "
wdenk1ebf41e2004-01-02 14:00:00 +0000159#endif
160
161#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenkb50cde52004-01-24 20:25:54 +0000162#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk1ebf41e2004-01-02 14:00:00 +0000163#else
wdenkb50cde52004-01-24 20:25:54 +0000164#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenk1ebf41e2004-01-02 14:00:00 +0000165#endif
wdenkb50cde52004-01-24 20:25:54 +0000166#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
167#define CFG_MAXARGS 16 /* max number of command args */
wdenk1ebf41e2004-01-02 14:00:00 +0000168#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
169
170#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
171#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
172
wdenkb50cde52004-01-24 20:25:54 +0000173#define CFG_LOAD_ADDR 0x100000 /* default load address */
wdenk1ebf41e2004-01-02 14:00:00 +0000174
wdenkb50cde52004-01-24 20:25:54 +0000175#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk1ebf41e2004-01-02 14:00:00 +0000176
177#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
178
179/*
180 * Low Level Configuration Settings
181 * (address mappings, register initial values, etc.)
182 * You should know what you are doing if you make changes here.
183 */
184/*-----------------------------------------------------------------------
185 * Internal Memory Mapped Register
186 */
187#define CFG_IMMR 0xFFF00000
188
189/*-----------------------------------------------------------------------
190 * Definitions for initial stack pointer and data area (in DPRAM)
191 */
192#define CFG_INIT_RAM_ADDR CFG_IMMR
wdenkb50cde52004-01-24 20:25:54 +0000193#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
194#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
wdenk1ebf41e2004-01-02 14:00:00 +0000195#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkb50cde52004-01-24 20:25:54 +0000196#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenk1ebf41e2004-01-02 14:00:00 +0000197
198/*-----------------------------------------------------------------------
199 * Start addresses for the final memory configuration
200 * (Set up by the startup code)
201 * Please note that CFG_SDRAM_BASE _must_ start at 0
202 */
wdenkb50cde52004-01-24 20:25:54 +0000203#define CFG_SDRAM_BASE 0x00000000
wdenk1ebf41e2004-01-02 14:00:00 +0000204#define CFG_FLASH_BASE 0x40000000
wdenkb50cde52004-01-24 20:25:54 +0000205#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk1ebf41e2004-01-02 14:00:00 +0000206#define CFG_MONITOR_BASE CFG_FLASH_BASE
wdenkb50cde52004-01-24 20:25:54 +0000207#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk1ebf41e2004-01-02 14:00:00 +0000208
209/*
210 * For booting Linux, the board info and command line data
211 * have to be in the first 8 MB of memory, since this is
212 * the maximum mapped by the Linux kernel during initialization.
213 */
wdenkb50cde52004-01-24 20:25:54 +0000214#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk1ebf41e2004-01-02 14:00:00 +0000215
216/*-----------------------------------------------------------------------
217 * FLASH organization
218 */
219#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
220#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
221
222#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
223#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
224
wdenkb50cde52004-01-24 20:25:54 +0000225#define CFG_ENV_IS_IN_FLASH 1
226#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
227#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
228#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenk1ebf41e2004-01-02 14:00:00 +0000229
230/* Address and size of Redundant Environment Sector */
231#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
232#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
233
234/*-----------------------------------------------------------------------
235 * Hardware Information Block
236 */
237#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
wdenkb50cde52004-01-24 20:25:54 +0000238#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
wdenk1ebf41e2004-01-02 14:00:00 +0000239#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
240
241/*-----------------------------------------------------------------------
242 * Cache Configuration
243 */
244#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
245#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
246#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
247#endif
248
249/*-----------------------------------------------------------------------
250 * SYPCR - System Protection Control 11-9
251 * SYPCR can only be written once after reset!
252 *-----------------------------------------------------------------------
253 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
254 */
255#if defined(CONFIG_WATCHDOG)
256#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
257 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
258#else
259#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
260#endif
261
262/*-----------------------------------------------------------------------
263 * SIUMCR - SIU Module Configuration 11-6
264 *-----------------------------------------------------------------------
265 * PCMCIA config., multi-function pin tri-state
266 */
wdenkb50cde52004-01-24 20:25:54 +0000267#ifndef CONFIG_CAN_DRIVER
wdenk1ebf41e2004-01-02 14:00:00 +0000268#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
269#else /* we must activate GPL5 in the SIUMCR for CAN */
270#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
271#endif /* CONFIG_CAN_DRIVER */
272
273/*-----------------------------------------------------------------------
274 * TBSCR - Time Base Status and Control 11-26
275 *-----------------------------------------------------------------------
276 * Clear Reference Interrupt Status, Timebase freezing enabled
277 */
278#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
279
280/*-----------------------------------------------------------------------
wdenk1ebf41e2004-01-02 14:00:00 +0000281 * PISCR - Periodic Interrupt Status and Control 11-31
282 *-----------------------------------------------------------------------
283 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
284 */
285#define CFG_PISCR (PISCR_PS | PISCR_PITF)
286
287/*-----------------------------------------------------------------------
wdenk1ebf41e2004-01-02 14:00:00 +0000288 * SCCR - System Clock and reset Control Register 15-27
289 *-----------------------------------------------------------------------
290 * Set clock output, timebase and RTC source and divider,
291 * power management and some other internal clocks
292 */
293#define SCCR_MASK SCCR_EBDF11
wdenkb50cde52004-01-24 20:25:54 +0000294#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenk1ebf41e2004-01-02 14:00:00 +0000295 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
296 SCCR_DFALCD00)
wdenk1ebf41e2004-01-02 14:00:00 +0000297
298/*-----------------------------------------------------------------------
299 * PCMCIA stuff
300 *-----------------------------------------------------------------------
301 *
302 */
303#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
304#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
305#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
306#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
307#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
308#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
309#define CFG_PCMCIA_IO_ADDR (0xEC000000)
310#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
311
312/*-----------------------------------------------------------------------
313 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
314 *-----------------------------------------------------------------------
315 */
316
wdenkb50cde52004-01-24 20:25:54 +0000317#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
wdenk1ebf41e2004-01-02 14:00:00 +0000318
wdenkb50cde52004-01-24 20:25:54 +0000319#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
320#undef CONFIG_IDE_LED /* LED for ide not supported */
wdenk1ebf41e2004-01-02 14:00:00 +0000321#undef CONFIG_IDE_RESET /* reset for ide not supported */
322
323#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
324#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
325
326#define CFG_ATA_IDE0_OFFSET 0x0000
327
328#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
329
330/* Offset for data I/O */
331#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
332
333/* Offset for normal register accesses */
334#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
335
336/* Offset for alternate registers */
337#define CFG_ATA_ALT_OFFSET 0x0100
338
339/*-----------------------------------------------------------------------
340 *
341 *-----------------------------------------------------------------------
342 *
343 */
wdenkb50cde52004-01-24 20:25:54 +0000344#define CFG_DER 0
wdenk1ebf41e2004-01-02 14:00:00 +0000345
346/*
347 * Init Memory Controller:
348 *
349 * BR0/1 and OR0/1 (FLASH)
350 */
351
352#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
353#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
354
355/* used to re-map FLASH both when starting from SRAM or FLASH:
356 * restrict access enough to keep SRAM working (if any)
357 * but not too much to meddle with FLASH accesses
358 */
359#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
360#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
361
362/*
wdenkb50cde52004-01-24 20:25:54 +0000363 * FLASH timing: Default value of OR0 after reset
wdenk1ebf41e2004-01-02 14:00:00 +0000364 */
wdenkb50cde52004-01-24 20:25:54 +0000365#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
366 OR_SCY_15_CLK | OR_TRLX)
wdenk1ebf41e2004-01-02 14:00:00 +0000367
368#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
369#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
370#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
371
372#define CFG_OR1_REMAP CFG_OR0_REMAP
373#define CFG_OR1_PRELIM CFG_OR0_PRELIM
374#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
375
376/*
377 * BR2/3 and OR2/3 (SDRAM)
378 *
379 */
380#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
381#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
wdenkb50cde52004-01-24 20:25:54 +0000382#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
wdenk1ebf41e2004-01-02 14:00:00 +0000383
384/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
385#define CFG_OR_TIMING_SDRAM 0x00000A00
386
387#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
388#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
389
wdenkb50cde52004-01-24 20:25:54 +0000390#ifndef CONFIG_CAN_DRIVER
391#define CFG_OR3_PRELIM CFG_OR2_PRELIM
wdenk1ebf41e2004-01-02 14:00:00 +0000392#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
393#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
wdenkb50cde52004-01-24 20:25:54 +0000394#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
wdenk1ebf41e2004-01-02 14:00:00 +0000395#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
396#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
397#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
398 BR_PS_8 | BR_MS_UPMB | BR_V )
399#endif /* CONFIG_CAN_DRIVER */
400
401/*
wdenkb50cde52004-01-24 20:25:54 +0000402 * 4096 Rows from SDRAM example configuration
403 * 1000 factor s -> ms
404 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
405 * 4 Number of refresh cycles per period
406 * 64 Refresh cycle in ms per number of rows
407 */
wdenk20bddb32004-09-28 17:59:53 +0000408#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
wdenkb50cde52004-01-24 20:25:54 +0000409
410/*
wdenk1ebf41e2004-01-02 14:00:00 +0000411 * Memory Periodic Timer Prescaler
wdenkb50cde52004-01-24 20:25:54 +0000412 * Periodic timer for refresh, start with refresh rate for 40 MHz clock
wdenk20bddb32004-09-28 17:59:53 +0000413 * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
wdenk1ebf41e2004-01-02 14:00:00 +0000414 */
wdenkb50cde52004-01-24 20:25:54 +0000415#define CFG_MAMR_PTA 39
wdenk1ebf41e2004-01-02 14:00:00 +0000416
417/*
418 * For 16 MBit, refresh rates could be 31.3 us
419 * (= 64 ms / 2K = 125 / quad bursts).
420 * For a simpler initialization, 15.6 us is used instead.
421 *
422 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
423 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
424 */
425#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
426#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
427
428/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
429#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
430#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
431
432/*
433 * MAMR settings for SDRAM
434 */
435
436/* 8 column SDRAM */
437#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
438 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
439 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
440/* 9 column SDRAM */
441#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
442 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
443 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkb50cde52004-01-24 20:25:54 +0000444/* 10 column SDRAM */
445#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
446 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
447 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenk1ebf41e2004-01-02 14:00:00 +0000448
449/*
450 * Internal Definitions
451 *
452 * Boot Flags
453 */
wdenkb50cde52004-01-24 20:25:54 +0000454#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenk1ebf41e2004-01-02 14:00:00 +0000455#define BOOTFLAG_WARM 0x02 /* Software reboot */
456
457#define CONFIG_SCC1_ENET
458#define CONFIG_FEC_ENET
459#define CONFIG_ETHPRIME "SCC ETHERNET"
460
461#endif /* __CONFIG_H */