Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
Gaurav Jain | 476c639 | 2022-03-24 11:50:35 +0530 | [diff] [blame] | 3 | * Copyright 2019, 2021 NXP |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <i2c.h> |
| 8 | #include <fdt_support.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 9 | #include <init.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 10 | #include <asm/global_data.h> |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 11 | #include <asm/io.h> |
| 12 | #include <asm/arch/clock.h> |
| 13 | #include <asm/arch/fsl_serdes.h> |
| 14 | #include <asm/arch/soc.h> |
| 15 | #include <asm/arch-fsl-layerscape/fsl_icid.h> |
| 16 | #include <hwconfig.h> |
| 17 | #include <ahci.h> |
| 18 | #include <mmc.h> |
| 19 | #include <scsi.h> |
| 20 | #include <fm_eth.h> |
| 21 | #include <fsl_csu.h> |
| 22 | #include <fsl_esdhc.h> |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 23 | #include <fsl_dspi.h> |
Stephen Carlson | 6fa0388 | 2021-06-22 16:40:27 -0700 | [diff] [blame] | 24 | #include "../common/i2c_mux.h" |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 25 | |
| 26 | #define LS1046A_PORSR1_REG 0x1EE0000 |
| 27 | #define BOOT_SRC_SD 0x20000000 |
| 28 | #define BOOT_SRC_MASK 0xFF800000 |
Pramod Kumar | 43f30ca | 2019-12-19 10:28:57 +0000 | [diff] [blame] | 29 | #define BOARD_REV_GPIO_SHIFT 17 |
| 30 | #define BOARD_REV_MASK 0x03 |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 31 | #define USB2_SEL_MASK 0x00000100 |
| 32 | |
| 33 | #define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \ |
| 34 | (((word) & 0x00ff0000) >> 8) | \ |
| 35 | (((word) & 0x0000ff00) << 8) | \ |
| 36 | (((word) & 0x000000ff) << 24)) |
| 37 | #define SPI_MCR_REG 0x2100000 |
| 38 | |
| 39 | DECLARE_GLOBAL_DATA_PTR; |
| 40 | |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 41 | static inline void demux_select_usb2(void) |
| 42 | { |
| 43 | u32 val; |
| 44 | struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR); |
| 45 | |
| 46 | val = in_be32(&pgpio->gpdir); |
| 47 | val |= USB2_SEL_MASK; |
| 48 | out_be32(&pgpio->gpdir, val); |
| 49 | |
| 50 | val = in_be32(&pgpio->gpdat); |
| 51 | val |= USB2_SEL_MASK; |
| 52 | out_be32(&pgpio->gpdat, val); |
| 53 | } |
| 54 | |
| 55 | static inline void set_spi_cs_signal_inactive(void) |
| 56 | { |
| 57 | /* default: all CS signals inactive state is high */ |
| 58 | uint mcr_val; |
| 59 | uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | |
| 60 | DSPI_MCR_CRXF | DSPI_MCR_CTXF; |
| 61 | |
| 62 | mcr_val = in_be32(SPI_MCR_REG); |
| 63 | mcr_val |= DSPI_MCR_HALT; |
| 64 | out_be32(SPI_MCR_REG, mcr_val); |
| 65 | out_be32(SPI_MCR_REG, mcr_cfg_val); |
| 66 | mcr_val = in_be32(SPI_MCR_REG); |
| 67 | mcr_val &= ~DSPI_MCR_HALT; |
| 68 | out_be32(SPI_MCR_REG, mcr_val); |
| 69 | } |
| 70 | |
| 71 | int board_early_init_f(void) |
| 72 | { |
| 73 | fsl_lsch2_early_init_f(); |
| 74 | |
| 75 | return 0; |
| 76 | } |
| 77 | |
| 78 | static inline uint8_t get_board_version(void) |
| 79 | { |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 80 | struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR); |
| 81 | |
Pramod Kumar | 43f30ca | 2019-12-19 10:28:57 +0000 | [diff] [blame] | 82 | /* GPIO 13 and GPIO 14 are used for Board Rev */ |
| 83 | u32 gpio_val = ((in_be32(&pgpio->gpdat) >> BOARD_REV_GPIO_SHIFT)) |
| 84 | & BOARD_REV_MASK; |
| 85 | |
| 86 | /* GPIOs' are 0..31 in Big Endiness, swap GPIO 13 and GPIO 14 */ |
| 87 | u8 val = ((gpio_val >> 1) | (gpio_val << 1)) & BOARD_REV_MASK; |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 88 | |
| 89 | return val; |
| 90 | } |
| 91 | |
| 92 | int checkboard(void) |
| 93 | { |
| 94 | static const char *freq[2] = {"100.00MHZ", "100.00MHZ"}; |
| 95 | u32 boot_src; |
| 96 | u8 rev; |
| 97 | |
| 98 | rev = get_board_version(); |
| 99 | switch (rev) { |
| 100 | case 0x00: |
| 101 | puts("Board: LS1046AFRWY, Rev: A, boot from "); |
| 102 | break; |
| 103 | case 0x01: |
| 104 | puts("Board: LS1046AFRWY, Rev: B, boot from "); |
| 105 | break; |
| 106 | default: |
| 107 | puts("Board: LS1046AFRWY, Rev: Unknown, boot from "); |
| 108 | break; |
| 109 | } |
| 110 | boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG)); |
| 111 | |
| 112 | if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD) |
| 113 | puts("SD\n"); |
| 114 | else |
| 115 | puts("QSPI\n"); |
| 116 | printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]); |
| 117 | |
| 118 | return 0; |
| 119 | } |
| 120 | |
| 121 | int board_init(void) |
| 122 | { |
Udit Agarwal | 22ec238 | 2019-11-07 16:11:32 +0000 | [diff] [blame] | 123 | #ifdef CONFIG_NXP_ESBC |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 124 | /* |
| 125 | * In case of Secure Boot, the IBR configures the SMMU |
| 126 | * to allow only Secure transactions. |
| 127 | * SMMU must be reset in bypass mode. |
| 128 | * Set the ClientPD bit and Clear the USFCFG Bit |
| 129 | */ |
| 130 | u32 val; |
| 131 | val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); |
| 132 | out_le32(SMMU_SCR0, val); |
| 133 | val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); |
| 134 | out_le32(SMMU_NSCR0, val); |
| 135 | #endif |
| 136 | |
Biwen Li | f0018f5 | 2020-02-05 22:02:17 +0800 | [diff] [blame] | 137 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 138 | return 0; |
| 139 | } |
| 140 | |
| 141 | int board_setup_core_volt(u32 vdd) |
| 142 | { |
| 143 | return 0; |
| 144 | } |
| 145 | |
| 146 | void config_board_mux(void) |
| 147 | { |
| 148 | #ifdef CONFIG_HAS_FSL_XHCI_USB |
| 149 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; |
| 150 | u32 usb_pwrfault; |
| 151 | /* |
| 152 | * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT |
| 153 | * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA |
| 154 | */ |
| 155 | out_be32(&scfg->rcwpmuxcr0, 0x3300); |
| 156 | #ifdef CONFIG_HAS_FSL_IIC3 |
| 157 | /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */ |
| 158 | out_be32(&scfg->rcwpmuxcr0, 0x0000); |
| 159 | #endif |
| 160 | out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); |
| 161 | usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << |
| 162 | SCFG_USBPWRFAULT_USB3_SHIFT) | |
| 163 | (SCFG_USBPWRFAULT_DEDICATED << |
| 164 | SCFG_USBPWRFAULT_USB2_SHIFT) | |
| 165 | (SCFG_USBPWRFAULT_SHARED << |
| 166 | SCFG_USBPWRFAULT_USB1_SHIFT); |
| 167 | out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); |
| 168 | #ifndef CONFIG_HAS_FSL_IIC3 |
| 169 | /* |
| 170 | * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input |
| 171 | * to select I2C3_USB2_SEL_IO |
| 172 | * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to |
| 173 | * I2C3 header (default) |
| 174 | * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to |
| 175 | * USB2 port |
| 176 | * programmed to select USB2 by setting GPIO3_23 output to one |
| 177 | */ |
| 178 | demux_select_usb2(); |
| 179 | #endif |
| 180 | #endif |
| 181 | set_spi_cs_signal_inactive(); |
| 182 | } |
| 183 | |
| 184 | #ifdef CONFIG_MISC_INIT_R |
| 185 | int misc_init_r(void) |
| 186 | { |
| 187 | config_board_mux(); |
| 188 | return 0; |
| 189 | } |
| 190 | #endif |
| 191 | |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 192 | int ft_board_setup(void *blob, struct bd_info *bd) |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 193 | { |
| 194 | u64 base[CONFIG_NR_DRAM_BANKS]; |
| 195 | u64 size[CONFIG_NR_DRAM_BANKS]; |
| 196 | |
| 197 | /* fixup DT for the two DDR banks */ |
| 198 | base[0] = gd->bd->bi_dram[0].start; |
| 199 | size[0] = gd->bd->bi_dram[0].size; |
| 200 | base[1] = gd->bd->bi_dram[1].start; |
| 201 | size[1] = gd->bd->bi_dram[1].size; |
| 202 | |
| 203 | fdt_fixup_memory_banks(blob, base, size, 2); |
| 204 | ft_cpu_setup(blob, bd); |
| 205 | |
| 206 | #ifdef CONFIG_SYS_DPAA_FMAN |
Madalin Bucur | b76b0a6 | 2020-04-23 16:25:19 +0300 | [diff] [blame] | 207 | #ifndef CONFIG_DM_ETH |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 208 | fdt_fixup_fman_ethernet(blob); |
| 209 | #endif |
Madalin Bucur | b76b0a6 | 2020-04-23 16:25:19 +0300 | [diff] [blame] | 210 | #endif |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 211 | |
| 212 | fdt_fixup_icid(blob); |
| 213 | |
| 214 | return 0; |
| 215 | } |