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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Feng Li39e112d2016-11-03 14:15:17 +08002/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
Gaurav Jain476c6392022-03-24 11:50:35 +05304 * Copyright 2021 NXP
Feng Li39e112d2016-11-03 14:15:17 +08005 */
6
7#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -07008#include <clock_legacy.h>
Simon Glass3bbe70c2019-12-28 10:44:54 -07009#include <fdt_support.h>
Simon Glassa7b51302019-11-14 12:57:46 -070010#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060011#include <net.h>
Feng Li39e112d2016-11-03 14:15:17 +080012#include <asm/arch/immap_ls102xa.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/fsl_serdes.h>
15#include <asm/arch/ls102xa_stream_id.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060016#include <asm/global_data.h>
Simon Glassdbd79542020-05-10 11:40:11 -060017#include <linux/delay.h>
Feng Li39e112d2016-11-03 14:15:17 +080018
19#include <asm/arch/ls102xa_devdis.h>
20#include <asm/arch/ls102xa_soc.h>
Feng Li39e112d2016-11-03 14:15:17 +080021#include <fsl_csu.h>
Feng Li39e112d2016-11-03 14:15:17 +080022#include <fsl_immap.h>
23#include <netdev.h>
24#include <fsl_mdio.h>
25#include <tsec.h>
26#include <spl.h>
27
28#include <fsl_validate.h>
29#include "../common/sleep.h"
30
31DECLARE_GLOBAL_DATA_PTR;
32
33#define DDR_SIZE 0x40000000
34
35
36int checkboard(void)
37{
38 puts("Board: LS1021AIOT\n");
39
40#ifndef CONFIG_QSPI_BOOT
41 struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
42 u32 cpldrev;
43
44 cpldrev = in_be32(&dcfg->gpporcr1);
45
46 printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
47 0xf));
48#endif
49 return 0;
50}
51
52void ddrmc_init(void)
53{
54 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
55 u32 temp_sdram_cfg, tmp;
56
57 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
58
59 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
60 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
61
62 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
63 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
64 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
65 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
66 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
67 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
68
69 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
70 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
71
72 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
73 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
74
75 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
76
77 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
78
79 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
80 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
81
82 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
83
84 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
85 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
86
87 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
88
89 /* DDR erratum A-009942 */
90 tmp = in_be32(&ddr->debug[28]);
91 out_be32(&ddr->debug[28], tmp | 0x0070006f);
92
93 udelay(500);
94
95 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
96
97 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
98}
99
100int dram_init(void)
101{
102#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
103 ddrmc_init();
104#endif
105
Alison Wangd6be97b2019-03-06 14:49:14 +0800106 erratum_a008850_post();
107
Feng Li39e112d2016-11-03 14:15:17 +0800108 gd->ram_size = DDR_SIZE;
109 return 0;
110}
111
Feng Li39e112d2016-11-03 14:15:17 +0800112int board_early_init_f(void)
113{
114 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
115
116#ifdef CONFIG_TSEC_ENET
117 /* clear BD & FR bits for BE BD's and frame data */
118 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
119 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
120
121#endif
122
123 arch_soc_init();
124
125 return 0;
126}
127
128#ifdef CONFIG_SPL_BUILD
129void board_init_f(ulong dummy)
130{
131 /* Clear the BSS */
132 memset(__bss_start, 0, __bss_end - __bss_start);
133
134 get_clocks();
135
136 preloader_console_init();
137
138 dram_init();
139
140 /* Allow OCRAM access permission as R/W */
141
142#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
143 enable_layerscape_ns_access();
144#endif
145
146 board_init_r(NULL, 0);
147}
148#endif
149
150int board_init(void)
151{
152#ifndef CONFIG_SYS_FSL_NO_SERDES
153 fsl_serdes_init();
154#endif
155
156 ls102xa_smmu_stream_id_init();
157
Feng Li39e112d2016-11-03 14:15:17 +0800158 return 0;
159}
160
161#ifdef CONFIG_BOARD_LATE_INIT
162int board_late_init(void)
163{
Feng Li39e112d2016-11-03 14:15:17 +0800164 return 0;
165}
166#endif
167
168#if defined(CONFIG_MISC_INIT_R)
169int misc_init_r(void)
170{
171#ifdef CONFIG_FSL_DEVICE_DISABLE
172 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
173
174#endif
Gaurav Jain476c6392022-03-24 11:50:35 +0530175 return 0;
Feng Li39e112d2016-11-03 14:15:17 +0800176}
177#endif
178
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900179int ft_board_setup(void *blob, struct bd_info *bd)
Feng Li39e112d2016-11-03 14:15:17 +0800180{
181 ft_cpu_setup(blob, bd);
182
183#ifdef CONFIG_PCI
184 ft_pci_setup(blob, bd);
185#endif
186
187 return 0;
188}
189
190void flash_write16(u16 val, void *addr)
191{
192 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
193
194 __raw_writew(shftval, addr);
195}
196
197u16 flash_read16(void *addr)
198{
199 u16 val = __raw_readw(addr);
200
201 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
202}