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git01.mediatek.com / filogic / uboot / b45315781e693c34de6b88c7c6249347a0bbbf93 / . / arch / arm / dts / imx8mm-cl-iot-gate.dts
blob: 425701204a0c393aec72d37e37902161bbd431c2 [file] [log] [blame]
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/usb/pd.h>
9#include "imx8mm.dtsi"
10
11/ {
12 model = "CompuLab IOT-GATE-iMX8";
13 compatible = "sb-iotgimx8", "cpl,ucm-imx8m-mini", "fsl,imx8mm-evk", "fsl,imx8mm";
14
15 chosen {
16 bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200";
17 stdout-path = &uart3;
18 };
19
Fabio Estevamf2acfc72022-04-12 13:05:37 -0300[diff] [blame]20 aliases {
21 eeprom0 = &i2c_eeprom0;
22 eeprom1 = &i2c_eeprom1;
23 };
24
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]25 reg_vusb_5v: regulator-usdhc2 {
26 compatible = "regulator-fixed";
27 regulator-name = "VUSB_5V";
28 regulator-min-microvolt = <5000000>;
29 regulator-max-microvolt = <5000000>;
30 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
31 regulator-boot-on;
32 enable-active-high;
33 };
34
35 reg_usdhc2_vqmmc: regulator-usdhc2_1v8 {
36 compatible = "regulator-fixed";
37 regulator-name = "usdhc2_1v8";
38 regulator-min-microvolt = <1800000>;
39 regulator-max-microvolt = <1800000>;
40 regulator-always-on;
41 };
42
43 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
44 compatible = "regulator-fixed";
45 regulator-name = "VSD_3V3";
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
48 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
49 enable-active-high;
50 startup-delay-us = <100>;
51 off-on-delay-us = <12000>;
52 };
53};
54
55&A53_0 {
56 cpu-supply = <&buck2_reg>;
57};
58
59&fec1 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_fec1>;
62 phy-mode = "rgmii-id";
63 phy-handle = <&ethphy0>;
64 fsl,magic-packet;
65 status = "okay";
66
67 mdio {
68 #address-cells = <1>;
69 #size-cells = <0>;
70
71 ethphy0: ethernet-phy@0 {
72 compatible = "ethernet-phy-ieee802.3-c22";
73 reg = <0>;
74 at803x,led-act-blind-workaround;
75 at803x,eee-okay;
76 at803x,vddio-1p8v;
77 };
78 };
79};
80
81&i2c1 {
82 clock-frequency = <400000>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_i2c1>;
85 status = "okay";
86
Fabio Estevamf2acfc72022-04-12 13:05:37 -0300[diff] [blame]87 i2c_eeprom0: eeprom@54 {
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]88 compatible = "atmel,24c08";
89 reg = <0x54>;
90 pagesize = <16>;
91 };
92};
93
94&i2c2 {
95 clock-frequency = <400000>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_i2c2>;
98 status = "okay";
99
Fabio Estevamf2acfc72022-04-12 13:05:37 -0300[diff] [blame]100 i2c_eeprom1: eeprom@50 {
101 compatible = "atmel,24c08";
102 reg = <0x50>;
103 pagesize = <16>;
104 };
Ying-Chun Liu (PaulLiu)01600c12021-04-22 04:50:30 +0800[diff] [blame]105 rtc@69 {
106 compatible = "abracon,ab1805";
107 reg = <0x69>;
108 pagesize = <16>;
109 status = "okay";
110 };
111
112 pmic@4b {
113 compatible = "rohm,bd71837";
114 reg = <0x4b>;
115 pinctrl-0 = <&pinctrl_pmic>;
116 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
117 interrupt-parent = <&gpio1>;
118 interrupts = <3 GPIO_ACTIVE_LOW>;
119
120 gpo {
121 rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
122 };
123
124 regulators {
125 bd71837,pmic-buck2-uses-i2c-dvs;
126 bd71837,pmic-buck2-dvs-voltage = <1000000>,
127 <900000>,
128 <0>; /* VDD_ARM: Run-Idle */
129 buck1_reg: BUCK1 {
130 regulator-name = "BUCK1";
131 regulator-min-microvolt = <700000>;
132 regulator-max-microvolt = <1300000>;
133 regulator-boot-on;
134 regulator-always-on;
135 regulator-ramp-delay = <1250>;
136 };
137
138 buck2_reg: BUCK2 {
139 regulator-name = "BUCK2";
140 regulator-min-microvolt = <700000>;
141 regulator-max-microvolt = <1300000>;
142 regulator-boot-on;
143 regulator-always-on;
144 regulator-ramp-delay = <1250>;
145 };
146
147 buck3_reg: BUCK3 {
148 regulator-name = "BUCK3";
149 regulator-min-microvolt = <700000>;
150 regulator-max-microvolt = <1350000>;
151 };
152
153 buck4_reg: BUCK4 {
154 regulator-name = "BUCK4";
155 regulator-min-microvolt = <700000>;
156 regulator-max-microvolt = <1350000>;
157 regulator-boot-on;
158 regulator-always-on;
159 };
160
161 buck5_reg: BUCK5 {
162 regulator-name = "BUCK5";
163 regulator-min-microvolt = <700000>;
164 regulator-max-microvolt = <1350000>;
165 regulator-boot-on;
166 regulator-always-on;
167 };
168
169 buck6_reg: BUCK6 {
170 regulator-name = "BUCK6";
171 regulator-min-microvolt = <3000000>;
172 regulator-max-microvolt = <3300000>;
173 regulator-boot-on;
174 regulator-always-on;
175 };
176
177 buck7_reg: BUCK7 {
178 regulator-name = "BUCK7";
179 regulator-min-microvolt = <1605000>;
180 regulator-max-microvolt = <1995000>;
181 regulator-boot-on;
182 regulator-always-on;
183 };
184
185 buck8_reg: BUCK8 {
186 regulator-name = "BUCK8";
187 regulator-min-microvolt = <800000>;
188 regulator-max-microvolt = <1400000>;
189 regulator-boot-on;
190 regulator-always-on;
191 };
192
193 ldo1_reg: LDO1 {
194 regulator-name = "LDO1";
195 regulator-min-microvolt = <3000000>;
196 regulator-max-microvolt = <3300000>;
197 regulator-boot-on;
198 regulator-always-on;
199 };
200
201 ldo2_reg: LDO2 {
202 regulator-name = "LDO2";
203 regulator-min-microvolt = <900000>;
204 regulator-max-microvolt = <900000>;
205 regulator-boot-on;
206 regulator-always-on;
207 };
208
209 ldo3_reg: LDO3 {
210 regulator-name = "LDO3";
211 regulator-min-microvolt = <1800000>;
212 regulator-max-microvolt = <3300000>;
213 regulator-boot-on;
214 regulator-always-on;
215 };
216
217 ldo4_reg: LDO4 {
218 regulator-name = "LDO4";
219 regulator-min-microvolt = <900000>;
220 regulator-max-microvolt = <1800000>;
221 regulator-boot-on;
222 regulator-always-on;
223 };
224
225 ldo5_reg: LDO5 {
226 regulator-name = "LDO5";
227 regulator-min-microvolt = <1800000>;
228 regulator-max-microvolt = <3300000>;
229 regulator-boot-on;
230 regulator-always-on;
231 };
232
233 ldo6_reg: LDO6 {
234 regulator-name = "LDO6";
235 regulator-min-microvolt = <900000>;
236 regulator-max-microvolt = <1800000>;
237 regulator-boot-on;
238 regulator-always-on;
239 };
240
241 ldo7_reg: LDO7 {
242 regulator-name = "LDO7";
243 regulator-min-microvolt = <1800000>;
244 regulator-max-microvolt = <3300000>;
245 };
246 };
247 };
248
249 ptn5110: tcpc@50 {
250 compatible = "nxp,ptn5110";
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_typec1>;
253 reg = <0x50>;
254 interrupt-parent = <&gpio2>;
255 interrupts = <11 8>;
256 status = "okay";
257
258 port {
259 typec1_dr_sw: endpoint {
260 remote-endpoint = <&usb1_drd_sw>;
261 };
262 };
263
264 typec1_con: connector {
265 compatible = "usb-c-connector";
266 label = "USB-C";
267 power-role = "dual";
268 data-role = "dual";
269 try-power-role = "sink";
270 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
271 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
272 PDO_VAR(5000, 20000, 3000)>;
273 op-sink-microwatt = <15000000>;
274 self-powered;
275 };
276 };
277};
278
279&i2c3 {
280 clock-frequency = <400000>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_i2c3>;
283 status = "disabled";
284};
285
286&i2c4 {/* Expansion connector I2C */
287 clock-frequency = <100000>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_i2c4>;
290 status = "okay";
291
292 pca9555: gpio@22 {
293 compatible = "nxp,pca9555";
294 reg = <0x22>;
295 gpio-controller;
296 #gpio-cells = <2>;
297 };
298};
299
300&snvs_pwrkey {
301 status = "okay";
302};
303
304&uart3 { /* console */
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_uart3>;
307 status = "okay";
308};
309
310&usbotg1 {
311 dr_mode = "host";
312 hnp-disable;
313 srp-disable;
314 adp-disable;
315 usb-role-switch;
316 vbus-supply = <&reg_vusb_5v>;
317 status = "okay";
318
319 port {
320 usb1_drd_sw: endpoint {
321 remote-endpoint = <&typec1_dr_sw>;
322 };
323 };
324};
325
326&usbotg2 {
327 dr_mode = "host";
328 status = "okay";
329};
330
331&usdhc2 {
332 pinctrl-names = "default", "state_100mhz", "state_200mhz";
333 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
334 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
335 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
336 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
337 bus-width = <4>;
338 fsl,wp-controller;
339 vmmc-supply = <&reg_usdhc2_vmmc>;
340 no-1-8-v;
341 mmc-ddr-1_8v;
342 non-removable;
343 vqmmc-supply = <&reg_usdhc2_vqmmc>;
344 status = "okay";
345};
346
347&usdhc3 {
348 pinctrl-names = "default", "state_100mhz";
349 pinctrl-0 = <&pinctrl_usdhc3>;
350 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
351 bus-width = <8>;
352 non-removable;
353 status = "okay";
354};
355
356&wdog1 {
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_wdog>;
359 fsl,ext-reset-output;
360 status = "okay";
361};
362
363&iomuxc {
364 pinctrl-names = "default";
365
366 pinctrl_hog: hoggrp {
367 fsl,pins = <
368 /* USB VBUS enable GPIO */
369 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x00
370 >;
371 };
372
373 pinctrl_hog_1: hoggrp-1 {
374 fsl,pins = <
375 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
376 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140
377 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x140
378 >;
379 };
380
381 pinctrl_fec1: fec1grp {
382 fsl,pins = <
383 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
384 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
385 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
386 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
387 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
388 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
389 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
390 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
391 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
392 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
393 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
394 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
395 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
396 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
397 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
398 >;
399 };
400
401 pinctrl_flexspi0: flexspi0grp {
402 fsl,pins = <
403 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
404 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
405 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
406 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
407 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
408 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
409 >;
410 };
411
412 pinctrl_i2c1: i2c1grp {
413 fsl,pins = <
414 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
415 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
416 >;
417 };
418
419 pinctrl_i2c2: i2c2grp {
420 fsl,pins = <
421 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
422 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
423 >;
424 };
425
426 pinctrl_i2c3: i2c3grp {
427 fsl,pins = <
428 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
429 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
430 >;
431 };
432
433 pinctrl_i2c4: i2c4grp {
434 fsl,pins = <
435 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
436 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
437 >;
438 };
439
440 pinctrl_pmic: pmicirq {
441 fsl,pins = <
442 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
443 >;
444 };
445
446 pinctrl_typec1: typec1grp {
447 fsl,pins = <
448 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
449 >;
450 };
451
452 pinctrl_uart3: uart1grp {
453 fsl,pins = <
454 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
455 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
456 >;
457 };
458
459 pinctrl_uart4: uart4grp {
460 fsl,pins = <
461 MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
462 MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
463 MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
464 MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
465 >;
466 };
467
468 pinctrl_usdhc2_gpio: usdhc2grpgpio {
469 fsl,pins = <
470 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
471 >;
472 };
473
474 pinctrl_usdhc2: usdhc2grp {
475 fsl,pins = <
476 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
477 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
478 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
479 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
480 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
481 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
482 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
483 >;
484 };
485
486 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
487 fsl,pins = <
488 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
489 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
490 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
491 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
492 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
493 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
494 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
495 >;
496 };
497
498 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
499 fsl,pins = <
500 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
501 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
502 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
503 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
504 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
505 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
506 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
507 >;
508 };
509
510 pinctrl_usdhc3: usdhc3grp {
511 fsl,pins = <
512 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
513 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
514 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
515 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
516 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
517 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
518 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
519 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
520 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
521 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
522 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
523 >;
524 };
525
526 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
527 fsl,pins = <
528 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
529 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
530 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
531 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
532 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
533 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
534 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
535 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
536 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
537 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
538 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
539 >;
540 };
541
542 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
543 fsl,pins = <
544 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
545 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
546 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
547 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
548 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
549 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
550 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
551 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
552 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
553 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
554 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
555 >;
556 };
557
558 pinctrl_wdog: wdoggrp {
559 fsl,pins = <
560 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
561 >;
562 };
563};