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Bo Shen58645902014-11-10 15:24:02 +08001/*
2 * Chip-specific header file for the SAMA5D4 SoC
3 *
4 * Copyright (C) 2014 Atmel
5 * Bo Shen <voice.shen@atmel.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __SAMA5D4_H
11#define __SAMA5D4_H
12
13/*
14 * defines to be used in other places
15 */
16#define CONFIG_AT91FAMILY /* It's a member of AT91 */
17
18/*
19 * Peripheral identifiers/interrupts.
20 */
21#define ATMEL_ID_FIQ 0 /* FIQ Interrupt */
22#define ATMEL_ID_SYS 1 /* System Controller */
23#define ATMEL_ID_ARM 2 /* Performance Monitor Unit */
24#define ATMEL_ID_PIT 3 /* Periodic Interval Timer */
25#define ATMEL_ID_WDT 4 /* Watchdog timer */
26#define ATMEL_ID_PIOD 5 /* Parallel I/O Controller D */
27#define ATMEL_ID_USART0 6 /* USART 0 */
28#define ATMEL_ID_USART1 7 /* USART 1 */
29#define ATMEL_ID_DMA0 8 /* DMA Controller 0 */
30#define ATMEL_ID_ICM 9 /* Integrity Check Monitor */
31#define ATMEL_ID_PKCC 10 /* Public Key Crypto Controller */
32#define ATMEL_ID_AES 12 /* Advanced Encryption Standard */
33#define ATMEL_ID_AESB 13 /* AES Bridge*/
34#define ATMEL_ID_TDES 14 /* Triple Data Encryption Standard */
35#define ATMEL_ID_SHA 15 /* SHA Signature */
36#define ATMEL_ID_MPDDRC 16 /* MPDDR controller */
37#define ATMEL_ID_MATRIX1 17 /* H32MX, 32-bit AHB Matrix */
38#define ATMEL_ID_MATRIX0 18 /* H64MX, 64-bit AHB Matrix */
39#define ATMEL_ID_VDEC 19 /* Video Decoder */
40#define ATMEL_ID_SBM 20 /* Secure Box Module */
41#define ATMEL_ID_SMC 22 /* Multi-bit ECC interrupt */
42#define ATMEL_ID_PIOA 23 /* Parallel I/O Controller A */
43#define ATMEL_ID_PIOB 24 /* Parallel I/O Controller B */
44#define ATMEL_ID_PIOC 25 /* Parallel I/O Controller C */
45#define ATMEL_ID_PIOE 26 /* Parallel I/O Controller E */
46#define ATMEL_ID_UART0 27 /* UART 0 */
47#define ATMEL_ID_UART1 28 /* UART 1 */
48#define ATMEL_ID_USART2 29 /* USART 2 */
49#define ATMEL_ID_USART3 30 /* USART 3 */
50#define ATMEL_ID_USART4 31 /* USART 4 */
51#define ATMEL_ID_TWI0 32 /* Two-Wire Interface 0 */
52#define ATMEL_ID_TWI1 33 /* Two-Wire Interface 1 */
53#define ATMEL_ID_TWI2 34 /* Two-Wire Interface 2 */
54#define ATMEL_ID_MCI0 35 /* High Speed Multimedia Card Interface 0 */
55#define ATMEL_ID_MCI1 36 /* High Speed Multimedia Card Interface 1 */
56#define ATMEL_ID_SPI0 37 /* Serial Peripheral Interface 0 */
57#define ATMEL_ID_SPI1 38 /* Serial Peripheral Interface 1 */
58#define ATMEL_ID_SPI2 39 /* Serial Peripheral Interface 2 */
59#define ATMEL_ID_TC0 40 /* Timer Counter 0 (ch. 0, 1, 2) */
60#define ATMEL_ID_TC1 41 /* Timer Counter 1 (ch. 3, 4, 5) */
61#define ATMEL_ID_TC2 42 /* Timer Counter 2 (ch. 6, 7, 8) */
62#define ATMEL_ID_PWMC 43 /* Pulse Width Modulation Controller */
63#define ATMEL_ID_ADC 44 /* Touch Screen ADC Controller */
64#define ATMEL_ID_DBGU 45 /* Debug Unit Interrupt */
65#define ATMEL_ID_UHPHS 46 /* USB Host High Speed */
66#define ATMEL_ID_UDPHS 47 /* USB Device High Speed */
67#define ATMEL_ID_SSC0 48 /* Synchronous Serial Controller 0 */
68#define ATMEL_ID_SSC1 49 /* Synchronous Serial Controller 1 */
69#define ATMEL_ID_XDMAC1 50 /* DMA Controller 1 */
70#define ATMEL_ID_LCDC 51 /* LCD Controller */
71#define ATMEL_ID_ISI 52 /* Image Sensor Interface */
72#define ATMEL_ID_TRNG 53 /* True Random Number Generator */
73#define ATMEL_ID_GMAC0 54 /* Ethernet MAC 0 */
74#define ATMEL_ID_GMAC1 55 /* Ethernet MAC 1 */
75#define ATMEL_ID_IRQ 56 /* IRQ Interrupt ID */
76#define ATMEL_ID_SFC 57 /* Fuse Controller */
77#define ATMEL_ID_SECURAM 59 /* Secured RAM */
78#define ATMEL_ID_SMD 61 /* SMD Soft Modem */
79#define ATMEL_ID_TWI3 62 /* Two-Wire Interface 3 */
80#define ATMEL_ID_CATB 63 /* Capacitive Touch Controller */
81#define ATMEL_ID_SFR 64 /* Special Funcion Register */
82#define ATMEL_ID_AIC 65 /* Advanced Interrupt Controller */
83#define ATMEL_ID_SAIC 66 /* Secured Advanced Interrupt Controller */
84#define ATMEL_ID_L2CC 67 /* L2 Cache Controller */
85
86/*
87 * User Peripherals physical base addresses.
88 */
89#define ATMEL_BASE_LCDC 0xf0000000
90#define ATMEL_BASE_DMAC1 0xf0004000
91#define ATMEL_BASE_ISI 0xf0008000
92#define ATMEL_BASE_PKCC 0xf000C000
93#define ATMEL_BASE_MPDDRC 0xf0010000
94#define ATMEL_BASE_DMAC0 0xf0014000
95#define ATMEL_BASE_PMC 0xf0018000
96#define ATMEL_BASE_MATRIX0 0xf001c000
97#define ATMEL_BASE_AESB 0xf0020000
98/* Reserved: 0xf0024000 - 0xf8000000 */
99#define ATMEL_BASE_MCI0 0xf8000000
100#define ATMEL_BASE_UART0 0xf8004000
101#define ATMEL_BASE_SSC0 0xf8008000
102#define ATMEL_BASE_PWMC 0xf800c000
103#define ATMEL_BASE_SPI0 0xf8010000
104#define ATMEL_BASE_TWI0 0xf8014000
105#define ATMEL_BASE_TWI1 0xf8018000
106#define ATMEL_BASE_TC0 0xf801c000
107#define ATMEL_BASE_GMAC0 0xf8020000
108#define ATMEL_BASE_TWI2 0xf8024000
109#define ATMEL_BASE_SFR 0xf8028000
110#define ATMEL_BASE_USART0 0xf802c000
111#define ATMEL_BASE_USART1 0xf8030000
112/* Reserved: 0xf8034000 - 0xfc000000 */
113#define ATMEL_BASE_MCI1 0xfc000000
114#define ATMEL_BASE_UART1 0xfc004000
115#define ATMEL_BASE_USART2 0xfc008000
116#define ATMEL_BASE_USART3 0xfc00c000
117#define ATMEL_BASE_USART4 0xfc010000
118#define ATMEL_BASE_SSC1 0xfc014000
119#define ATMEL_BASE_SPI1 0xfc018000
120#define ATMEL_BASE_SPI2 0xfc01c000
121#define ATMEL_BASE_TC1 0xfc020000
122#define ATMEL_BASE_TC2 0xfc024000
123#define ATMEL_BASE_GMAC1 0xfc028000
124#define ATMEL_BASE_UDPHS 0xfc02c000
125#define ATMEL_BASE_TRNG 0xfc030000
126#define ATMEL_BASE_ADC 0xfc034000
127#define ATMEL_BASE_TWI3 0xfc038000
128
Bo Shendc1fdb22014-12-15 13:24:33 +0800129#define ATMEL_BASE_MATRIX1 0xfc054000
130
Bo Shen58645902014-11-10 15:24:02 +0800131#define ATMEL_BASE_SMC 0xfc05c000
132#define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070)
133#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500)
134
135#define ATMEL_BASE_PIOD 0xfc068000
136#define ATMEL_BASE_RSTC 0xfc068600
137#define ATMEL_BASE_PIT 0xfc068630
138#define ATMEL_BASE_WDT 0xfc068640
139
140#define ATMEL_BASE_DBGU 0xfc069000
141#define ATMEL_BASE_PIOA 0xfc06a000
142#define ATMEL_BASE_PIOB 0xfc06b000
143#define ATMEL_BASE_PIOC 0xfc06c000
144#define ATMEL_BASE_PIOE 0xfc06d000
145#define ATMEL_BASE_AIC 0xfc06e000
146
Wenyou Yang0a248bc2015-09-08 14:38:26 +0800147#define ATMEL_CHIPID_CIDR 0xfc069040
148#define ATMEL_CHIPID_EXID 0xfc069044
149
Bo Shen58645902014-11-10 15:24:02 +0800150/*
151 * Internal Memory.
152 */
153#define ATMEL_BASE_ROM 0x00000000 /* Internal ROM base address */
154#define ATMEL_BASE_NFC 0x00100000 /* NFC SRAM */
155#define ATMEL_BASE_SRAM 0x00200000 /* Internal ROM base address */
156#define ATMEL_BASE_VDEC 0x00300000 /* Video Decoder Controller */
157#define ATMEL_BASE_UDPHS_FIFO 0x00400000 /* USB Device HS controller */
158#define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller (OHCI) */
159#define ATMEL_BASE_EHCI 0x00600000 /* USB Host controller (EHCI) */
160#define ATMEL_BASE_AXI 0x00700000
161#define ATMEL_BASE_DAP 0x00800000
162#define ATMEL_BASE_SMD 0x00900000
163
164/*
165 * External memory
166 */
167#define ATMEL_BASE_CS0 0x10000000
168#define ATMEL_BASE_DDRCS 0x20000000
169#define ATMEL_BASE_CS1 0x60000000
170#define ATMEL_BASE_CS2 0x70000000
171#define ATMEL_BASE_CS3 0x80000000
172
173/*
174 * Other misc defines
175 */
176#define ATMEL_PIO_PORTS 5
177#define CPU_HAS_PIO3
178#define PIO_SCDR_DIV 0x3fff
179#define CPU_HAS_PCR
180#define CPU_HAS_H32MXDIV
181
Wenyou Yang335cdff2015-11-05 16:37:52 +0800182/* MATRIX0(H64MX) slave id definitions */
183#define H64MX_SLAVE_AXIMX_BRIDGE 0 /* Bridge from H64MX to AXIMX */
184#define H64MX_SLAVE_PERIPH_BRIDGE 1 /* H64MX Peripheral Bridge */
185#define H64MX_SLAVE_VDEC 2 /* Video Decoder */
186#define H64MX_SLAVE_DDRC_PORT0 3 /* DDR2 Port0-AESOTF */
187#define H64MX_SLAVE_DDRC_PORT1 4 /* DDR2 Port1 */
188#define H64MX_SLAVE_DDRC_PORT2 5 /* DDR2 Port2 */
189#define H64MX_SLAVE_DDRC_PORT3 6 /* DDR2 Port3 */
190#define H64MX_SLAVE_DDRC_PORT4 7 /* DDR2 Port4 */
191#define H64MX_SLAVE_DDRC_PORT5 8 /* DDR2 Port5 */
192#define H64MX_SLAVE_DDRC_PORT6 9 /* DDR2 Port6 */
193#define H64MX_SLAVE_DDRC_PORT7 10 /* DDR2 Port7 */
194#define H64MX_SLAVE_SRAM 11 /* Internal SRAM 128K */
195#define H64MX_SLAVE_H32MX_BRIDGE 12 /* Bridge from H64MX to H32MX */
196
197/* MATRIX1(H32MX) slave id definitions */
198#define H32MX_SLAVE_H64MX_BRIDGE 0 /* Bridge from H32MX to H64MX */
199#define H32MX_SLAVE_PERIPH_BRIDGE0 1 /* H32MX Peripheral Bridge 0 */
200#define H32MX_SLAVE_PERIPH_BRIDGE1 2 /* H32MX Peripheral Bridge 1 */
201#define H32MX_SLAVE_EBI 3 /* External Bus Interface */
202#define H32MX_SLAVE_NFC_CMD 3 /* NFC command Register */
203#define H32MX_SLAVE_NFC_SRAM 4 /* NFC SRAM */
204#define H32MX_SLAVE_USB 5 /* USB Device & Host */
205#define H32MX_SLAVE_SMD 6 /* Soft Modem (SMD) */
206
Wenyou Yangedf88d32015-11-05 16:37:53 +0800207/* AICREDIR Unlock Key */
208#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
209
Bo Shen58645902014-11-10 15:24:02 +0800210/* sama5d4 series chip id definitions */
211#define ARCH_ID_SAMA5D4 0x8a5c07c0
212#define ARCH_EXID_SAMA5D41 0x00000001
213#define ARCH_EXID_SAMA5D42 0x00000002
214#define ARCH_EXID_SAMA5D43 0x00000003
215#define ARCH_EXID_SAMA5D44 0x00000004
216
217#define cpu_is_sama5d4() (get_chip_id() == ARCH_ID_SAMA5D4)
218#define cpu_is_sama5d41() (cpu_is_sama5d4() && \
219 (get_extension_chip_id() == ARCH_EXID_SAMA5D41))
220#define cpu_is_sama5d42() (cpu_is_sama5d4() && \
221 (get_extension_chip_id() == ARCH_EXID_SAMA5D42))
222#define cpu_is_sama5d43() (cpu_is_sama5d4() && \
223 (get_extension_chip_id() == ARCH_EXID_SAMA5D43))
224#define cpu_is_sama5d44() (cpu_is_sama5d4() && \
225 (get_extension_chip_id() == ARCH_EXID_SAMA5D44))
226
Bo Shendf1555d2015-02-04 15:53:02 +0800227/* Timer */
228#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
229
Bo Shen58645902014-11-10 15:24:02 +0800230/*
231 * No PMECC Galois table in ROM
232 */
233#define NO_GALOIS_TABLE_IN_ROM
234
235#ifndef __ASSEMBLY__
236unsigned int get_chip_id(void);
237unsigned int get_extension_chip_id(void);
238unsigned int has_lcdc(void);
239char *get_cpu_name(void);
240#endif
241
242#endif