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git01.mediatek.com / filogic / uboot / b42bbc25c78c791d2819a40518cd0eb9c71474da / . / arch / arm / dts / fsl-ls2080a-qds.dts
blob: 0a7f1ffb2db39cac2caf62c10c7bf6c0f1b77d96 [file] [log] [blame]
Haikun Wang94c21bb2015-06-26 19:48:58 +0800[diff] [blame]1/*
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530[diff] [blame]2 * Freescale ls2080a QDS board device tree source
Haikun Wang94c21bb2015-06-26 19:48:58 +0800[diff] [blame]3 *
4 * Copyright 2013-2015 Freescale Semiconductor, Inc.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9/dts-v1/;
10
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530[diff] [blame]11#include "fsl-ls2080a.dtsi"
Haikun Wang94c21bb2015-06-26 19:48:58 +0800[diff] [blame]12
13/ {
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530[diff] [blame]14 model = "Freescale Layerscape 2080a QDS Board";
15 compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
Haikun Wang94c21bb2015-06-26 19:48:58 +0800[diff] [blame]16
17 aliases {
Yuan Yaob42bbc22016-06-08 18:24:56 +0800[diff] [blame^]18 spi0 = &qspi;
Haikun Wang94c21bb2015-06-26 19:48:58 +0800[diff] [blame]19 spi1 = &dspi;
20 };
21};
22
23&dspi {
24 bus-num = <0>;
25 status = "okay";
26
27 dflash0: n25q128a {
28 #address-cells = <1>;
29 #size-cells = <1>;
30 compatible = "spi-flash";
31 spi-max-frequency = <3000000>;
32 spi-cpol;
33 spi-cpha;
34 reg = <0>;
35 };
36 dflash1: sst25wf040b {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "spi-flash";
40 spi-max-frequency = <3000000>;
41 spi-cpol;
42 spi-cpha;
43 reg = <1>;
44 };
45 dflash2: en25s64 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "spi-flash";
49 spi-max-frequency = <3000000>;
50 spi-cpol;
51 spi-cpha;
52 reg = <2>;
53 };
54};
Yuan Yaob42bbc22016-06-08 18:24:56 +0800[diff] [blame^]55
56&qspi {
57 bus-num = <0>;
58 status = "okay";
59
60 qflash0: s25fs256s@0 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "spi-flash";
64 spi-max-frequency = <20000000>;
65 reg = <0>;
66 };
67};